Discussion Intel current and future Lakes & Rapids thread

[igor_kavinski]

Judgement tbd on Skymont, but LNC looks pretty bad indeed.

ARL bad. LNC also bad.

Why does it seem like you are trying to scare people into selling off their Intel stock prematurely?

 

[Geddagod]

No, I'm being serious for once.
Judgement tbd on Skymont, but LNC looks pretty bad indeed.

Reverse Conroe situation for Intel is gonna suck, but I don't think it's DOA worthy. Intel still has its OEMs to bribe convince to sell, and I don't think ARL will be that far behind in efficiency (if at all) in the mobile space either- so even if AMD starts trying really hard for mobile with Zen 5, I doubt it's going to start really hurting for Intel.
It will suck, and ye Intel in DIY is going to suck too (esp since you can't price TSMC 3nm and advanced packaging cheap) but I'm seeing this as a reverse ADL situation. At the very least, Intel fanbois will have some reason to upgrade over RPL-R. Stuff like RKL/Bulldozer don't even get that honor.

 

[adroc_thurston]

Well, you can't say that

Yea I can, the design reeked for Sun Niagara and that wasn't good at all.

it's a blunder that RDNA 3's doubled up FP units aren't even taken advantage of in many workloads

Yes they are, just that doubling the issue on 4-port vRF is pretty hard.

I'm sure AMD will optimize drivers for the computing power of RDNA 3 but the fact that the hardware is underutilized is very much a Bulldozer-esque moment.

No.

Why does it seem like you are trying to scare people into selling off their Intel stock prematurely?

Focus on CWF instead, looks promising.

but I don't think it's DOA worthy.

The -S one definitely is.

I don't think ARL will be that far behind in efficiency (if at all) in the mobile space eithe

I have quite some news for you indeed.

so even if AMD starts trying really hard for mobile with Zen 5, I doubt it's going to start really hurting for Intel.

Eh.

 

[H433x0n]

and I don't think ARL will be that far behind in efficiency (if at all) in the mobile space either- so even if AMD starts trying really hard for mobile with Zen 5, I doubt it's going to start really hurting for Intel.

Mobile is the one segment that I’m not concerned with at all. Everything here from on out looks pretty solid in that market (MTL, ARL, LNL).

At the very least, Intel fanbois will have some reason to upgrade over RPL-R. Stuff like RKL/Bulldozer don't even get that honor.

I think you’d be surprised. If it performs that poorly I personally see no reason to buy it. A 1-3% ST performance gain on a chip that overclocks like crap on TSMC silicon? No thanks.

 

[mikk]

RWC in GNR is not identical to RWC in MTL. There’s almost always changes from client to server cores. Usually they’re relatively minor and have to do with cache layout and optimizing packaging but nonetheless there are changes. I mean, you could technically call EMR cores a sort of RPC+. MLID claiming a +10% IPC increase was never really a physical possibility given the modest improvements from RPC (as you know).

An improvement of 3-6% for Specfp and 4-8% for Specint is in the realm of RWC improvements over RPC.

What about 6-7% over Raptor Cove (mixed Int+FP)? There is one chinese source who said 8-9% over Golden Cove in mixed Int+FP.

 

[H433x0n]

What about 6-7% over Raptor Cove (mixed Int+FP)? There is one chinese source who said 8-9% over Golden Cove in mixed Int+FP.

If that were true, then it’s sort of sad since I’m fairly certain they would’ve been better off just rolling with a MTL refresh. A MTL refresh on Intel 3 could possibly achieve 5.4-5.6ghz clocks and perform like ARL.

 

[Abwx]

The y-axis is perf per thread.

Perf per thread but no scale has no significance, that s just random lines...

 

[H433x0n]

Perf per thread but no scale has no significance, that s just random lines...

Right next to the graph there’s a statement of 240% improvement in perf/watt.

 

[H433x0n]

Interesting article.

Not sure what Digitimes track record is but there's some interesting tidbits.

According to the semiconductor supply chain, the original performance of 3nm can be better, mainly because Intel (Intel) adjusted the platform blueprint schedule, and the contribution to TSMC's revenue was reduced and deferred.

However, with Intel's launch of the internal dismantling plan in June, the design and manufacturing departments have climbed the mountain with their own efforts, and the plan of outsourcing TSMC has become more established, and the two sides will cooperate more closely in the Arrow Lake generation in 6, and there will be two versions in parallel.

It is understood that Arrow Lake, which will be launched in the second half of 2024, is currently rumored to be revised by the production blueprint, and will adopt a dual version, in addition to the U series and other CPUs will skip the Intel 20A process and change to Intel 3, the top H / HX series CPUs will use TSMC N3 family foundry

All of this was translated so there can be some context missing.

 

[Khato]

A 240% improvement in general compute perf/watt combined with the accelerators which have been their current lone competitive advantage is going to make Sierra Forest quite the compelling option for certain customers. Might even be adequate for Intel DCAI to start posting positive net income again in addition to reclaiming market share.

 

[Doug S]

Yeah, the rumors say that LNC has pretty high IPC gains, like 30-40%, but it tops out at like low to mid 4 GHz, which essentially nullifies the IPC gains in the desktop market. However, since servers don't clock their cores all that high to begin with, LNC in the server space shouldn't be too bad... that is assuming the bigger core doesn't burn a ton of power, thus leading to a clock regression even in the server space.

Given that you can't just keep increasing clock rate without consequences for power draw (the frequency wall is real - there's a reason the clock ceiling has been in the 5 to 6 GHz range since the Pentium 4 days) once you top out you can either make small IPC improvements and keep clock rate the same or you can take a major IPC step that requires sacrificing clock rate and start down the path of slowly increasing frequency in each generation until you reach the wall once again.

Intel already did this once, though I can't be bothered to remember all their code names so I'll have to have someone else recall which generation did this last time.

 

[mikk]

Interesting article.

Not sure what Digitimes track record is but there's some interesting tidbits.


All of this was translated so there can be some context missing.

This makes sense to me:

In addition to the U-series CPUs, which will skip the Intel 20A process and be replaced by Intel 3

This is however a refreshed Meteor Lake and if digitimes is accurate an Intel 3 refresh of Meteor Lake. Because they have a server variant of RWC+CMT on Intel 3 they can do this without much effort. I don't think we will see LNC on Intel 3. Also Intel confirmed there are two different microarchitectures in the Arrow Lake family (06_C5H, 06_C6H). Only C6H supports the new instructions from Lion Cove and Skymont. At the moment only Arrow Lake S is using the real one. If all goes wrong they could use a refreshed Meteor Lake for the entire mobile lineup.

top H/HX-series CPUs will use TSMC's N3 family for OEM production

Top refers to 8+16? It is no news that it's using TSMC N3. The only one rumored tile using 20A was 6+8. It's not clear if it's desktop only or for mobile as well. 6+8 would make sense for mobile but who knows.

 

[SiliconFly]

Is that a thing? I personally haven't felt like people are using Bulldozer as a meme at the moment...

But yeah, a Bulldozer moment is when there's an overhaul of the architecture that sounds great on paper but the execution or physical implementation sucks. In my opinion, it doesn't even have to be an ambitious architecture; it just needs to be a paradigm shift that goes awry.

Raptorlake is definitely not a Bulldozer moment, but RDNA 3 would be.

Well, I'm not saying LNC is bad. It looks great on paper. But has the potential to be the Bulldozer moment for Intel. Just sayin'

 

[uzzi38]

If that were true, then it’s sort of sad since I’m fairly certain they would’ve been better off just rolling with a MTL refresh. A MTL refresh on Intel 3 could possibly achieve 5.4-5.6ghz clocks and perform like ARL.

Well we'll be able to put this one to the test.

Sort of, anyway.

 

[JoeRambo]

Intel seems to be doing some minor, but nice changes with P-Core in GNR:

64KB 16-Way L1I is logical move as code size has been growing. "VM" style languages like Python, Java, JS are also gonna benefit from this. I think it finally dawned to Intel that uCode caches are great, but they don't have to buy in their marketing word for hit rates. I wonder about energy costs, 16-way not cheap, but again they are probably throwing transistors at the problem.
Improved branch predictions is marketing slide point, going since Z80 times, probably minor unless Chips And Cheese finds otherwise.
3 cycle latency FP multiplication is minor but nice, AMD had it already and Intel's 4 cycle was just being lazy and convenient having same latency as FMA. No point leaving perf on table.
More outstanding memory misses and prefetch => very common sense change to have in your core when your L3 cache is designed by monkeys escaped from San Diego zoo and has 50ns latency. I find it funny they had to do the same in E-Core, at 64 L2 miss queue size their new "Atom" is handily beating Golden Cove that had only 48.

 

[eek2121]

Also is it just me, or are people completely over using the "bulldozer moment" meme online? AFAIK, a bulldozer moment is a ambitious arch that was often a regression vs its predecessor that just completely fails to compete as well. I heard people describing RPL-R as a "bulldozer moment" online and I was like ??? Perhaps I'm too liberal with it too, but calling RPL-R a "bulldozer moment" just seems extreme...

I don’t know, but I will say this: Bulldozer wasn’t bad as a concept, AMD just mucked up execution.

If AMD made a bulldozer type design today things would look completely different.

I still wish companies would explore CMT.

A 240% improvement in general compute perf/watt combined with the accelerators which have been their current lone competitive advantage is going to make Sierra Forest quite the compelling option for certain customers. Might even be adequate for Intel DCAI to start posting positive net income again in addition to reclaiming market share.

Intel is going to support 8 sockets, which is absolute insanity. 480 cores in a 4U? Cloud computing in a box.

 

[igor_kavinski]

Intel seems to be doing some minor, but nice changes with P-Core in GNR

Improved IPC in RWC but pointless if they can't manage minimum 5.8 GHz in ST workloads.

 

[SiliconFly]

Interesting Battlemage news today. ES spotted. Looks like Arrow Lake is getting Battlemage after all...

 

[Joe NYC]

The y-axis is perf per thread.

So, on average, less than 50% performance per SPR thread, while SPR has SMT?

That doesn't seem right. In fact, that would be awful performance, if this is a correct interpretation.

 

[igor_kavinski]

Looks like Arrow Lake is getting Battlemage after all...

Might be the only good thing about it, especially if it has potent raytracing perf for an iGPU.

 

[lightisgood]

Intel's 'Meteor Lake' CPU power will be controlled by AI

An AI-controlled algorithm will govern how Intel's upcoming Meteor Lake chip will swing between high-power processing states and low-power sleep states, making it more responsive and saving power.

www.pcworld.com

By only implementing advanced power management, MTL achieves 10~20% long battery life.
There is no room for doubt that MTL has great competitiveness.

 

[Joe NYC]

I’m just going off of the general internet / anandtech consensus that LNC is DOA or “stillborn”. I don’t have any concrete insider info to say otherwise even though I’m pretty skeptical Intel would willing head straight into a disaster product launch.

Whatever the next CPU package, it will have a number of things, including CPU, iGPU, connectivity, some AI gimmick, support for the next platform.

There is no other option than to proceed with it, even if the CPU component is underdelivering.

 

[Joe NYC]

If it is indeed the case, that Arrow Lake will use Intel 3 in one of its versions instead of 20A, it makes a lot of sense to me. In fact, I thought it was dumb for Intel to pin its roadmap on a node that is so far out, instead of a node that should be a lot more solid at the anticipated time of the release.

 

[Joe NYC]

This slide should put to rest the theory that Sierra Forrest will have multiples of the 144 cores. This tweet says that 288 cores would be available - in 2 socket servers:

https://twitter.com/x/status/1696315800792309934

 

[Geddagod]

Is that a thing? I personally haven't felt like people are using Bulldozer as a meme at the moment...

Hop on Reddit lol

Looks like Arrow Lake is getting Battlemage after all...

BMG was always going to get ready at a similar time as ARL's alchemist GPU tile, since LNL uses BMG as well. Besides, the BMG spotted was BMG G-10, which based on previous leaks, was a discrete GPU, not part of any iGPU.

By only implementing advanced power management, MTL achieves 10~20% long battery life.
There is no room for doubt that MTL has great competitiveness.

Intel is going to need to like 80% more battery life to match AMD. There's plenty of room to doubt.

f it is indeed the case, that Arrow Lake will use Intel 3 in one of its versions instead of 20A, it makes a lot of sense to me.

ARL on Intel 3 is in reference to MTL being refreshed for ARL-U. It's literally just MTL on Intel 3, but it's being called ARL-U. But that's just a rumor.
We won't be seeing LNC on Intel 3, and if we did, we would have seen it on GNR anyway.