DrMrLordX
Lifer
- Apr 27, 2000
- 22,921
- 12,993
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Maybe Meteor Lake suffers significant losses to efficiency at clocks nearing 5 GHz. Just because you can get it running at 4.8 GHz, may not mean that you'll like it when you get there.
Maybe the E cores get a separate voltage rail, this is the most obvious power architecture flaw on current hybrid beside the high uncore power draw.
If the performance is at the level of RPL, with 50% better efficiency, and the iGPU is 2x better, it will be competitive with the AMD Phoenix, and therefore good. I am waiting for something from those two for a new laptop.
GNR uses RWC (not RWC+ or whatever), and for SRF Sierra Glenn looks to just be Gracemont ported over to Intel 3
adroc_thurston
Diamond Member
- Jul 2, 2023
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RWC+ just means it got ported over to i3.
That's the new intel plus definition.
I don't know if these numbers are correct, but if they are, Intel is not really serious about any sort of large scale transition to MTL
It's almost as if Intel was just dipping its toes in the Meteor Lake.
wccftech.com
It's almost as if Intel was just dipping its toes in the Meteor Lake.
Intel Could Dish Out An Estimated 365,000 Next-Gen Meteor Lake CPU Tiles Per Month
It is being said by industry sources that Intel for now can achieve a maximum output of 365,000 Meteor Lake CPU tiles per month.
wccftech.com
That's assuming 50% yield. TGL-H shipped 1 million units before launch and MTL also seemed to have ramped a couple months before it will launch too, so I assume similar volume. Depending on how fast they ramp it could end up being decent volume as we pass 2023.I don't know if these numbers are correct, but if they are, Intel is not really serious about any sort of large scale transition to MTL
It's almost as if Intel was just dipping its toes in the Meteor Lake.
Intel Could Dish Out An Estimated 365,000 Next-Gen Meteor Lake CPU Tiles Per Month
It is being said by industry sources that Intel for now can achieve a maximum output of 365,000 Meteor Lake CPU tiles per month.
Sierra Glenn gets a new name though for some reason, but RWC in GNR doesn't?
As for RWC+ I'm referencing Tom's "RWC+ being 10% higher IPC than RWC" leak lol
adroc_thurston
Diamond Member
- Jul 2, 2023
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Had to implement DC-level RAS features which vanilla Gracemont doesn't have.
(you can look at Avoton vs Broadwell-D RAS comparison table to get a rough idea of what Atom lacks vs big boy cores).
who's tom? the cat?
Saylick
Diamond Member
- Sep 10, 2012
- 4,052
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Given that the compute dies are pretty small, they should be able to pump out more of those dies per month. I'm starting to think that advanced packaging is the real limiter of MTL volume. It doesn't help that Intel is also using advanced packaging for some of their server parts, so something's got to give.I don't know if these numbers are correct, but if they are, Intel is not really serious about any sort of large scale transition to MTL
It's almost as if Intel was just dipping its toes in the Meteor Lake.
Intel Could Dish Out An Estimated 365,000 Next-Gen Meteor Lake CPU Tiles Per Month
It is being said by industry sources that Intel for now can achieve a maximum output of 365,000 Meteor Lake CPU tiles per month.
adroc_thurston
Diamond Member
- Jul 2, 2023
- 7,192
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It's a margin death part that doesn't win anything relevant so they're not gonna make many of these.
RPL-U 282 will be the volume driver way into 2025, kek.
I don't know if these numbers are correct, but if they are, Intel is not really serious about any sort of large scale transition to MTL
It's almost as if Intel was just dipping its toes in the Meteor Lake.
Intel Could Dish Out An Estimated 365,000 Next-Gen Meteor Lake CPU Tiles Per Month
It is being said by industry sources that Intel for now can achieve a maximum output of 365,000 Meteor Lake CPU tiles per month.
This writer dose'nt have any reliable number.
> Finally, he said, EUV production capacity has been secured enough to meet market demand
This is.
P.S.
His delusion came from false understanding about fab D1.
D1 is not only process development fab but also manufacturing.
Meteor Lakeは歩留まりが50%でも月産約36万個 インテル CPUロードマップ (2/2)
8月21日から25日にかけて、マレーシアでIntel TECH tour.MYが開催された。この中で説明があったMeteor Lake関連の話を説明したい。
> I don't know how many Intel 4s are mass-produced in D1, but D1 is all process development factories and they are forced to mass-produce using them, so there is at most one line that can be devoted to 4nm mass production.
> Even 4,000 sheets per month is suspicious, about 1,000.
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Like it was mentioned before, Wccftech is bottom barrel trash. Don't take them seriously.I don't know if these numbers are correct, but if they are, Intel is not really serious about any sort of large scale transition to MTL
It's almost as if Intel was just dipping its toes in the Meteor Lake.
Intel Could Dish Out An Estimated 365,000 Next-Gen Meteor Lake CPU Tiles Per Month
It is being said by industry sources that Intel for now can achieve a maximum output of 365,000 Meteor Lake CPU tiles per month.
Intel said last month that Intel 4 yields are excellent and the dies per wafer should be well above 600.
And by the end of sept, they should already have one or two million tiles ready. Thats plenty enough to start.
It is likely correct since Intel invited wccftech to their presentations a few times. I did read an interestiing opinion the other morning about the future of e cores and how intel plans to include more o fthem in future. I didn't save the web page but the crux of the long writeup was whether or not intel adds more e cores there abilitiy to be used lies in the hands of both developers and microsoft if were to assume windows remains the largest personal computing platform over the next decade. this is a safe bet. itd or intel thread director can do only so much on chip but the software end needs to pick up the slack.
The yield was just a guestimate (unimportant part of the article)
The story is the low number of wafer starts.
The number of wafer was just a guestimate (important part of the article).
dullard
Elite Member
- May 21, 2001
- 26,024
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That is quite true. The CPU can only suggest to Windows what to do and Windows gets to override that suggestion. Windows has information on the software and user settings, but can only estimate the best way to handle it. But, if software sets the flag of which type of core to use for each thread, then the optimum solution is usually found. It isn't usually a difficult software change, but it is a software change.
For example, Outlook should normally send/receive emails on the E cores. There is no reason an incoming email should take precedence over what you are currently working on. That is, unless the user clicks the Send/Receive button, in which case this should be a priority on the P core. That is a software change that Windows and the CPU could not readily know to do.
Background virus scans should be on E cores. Foreground virus scans on P cores. Etc. The software developers know far better what should be a priority than generic algorithms ever will.
I don't see this really changing quickly though. Especially not until AMD also has hybrid cores late next year. Why would a software developer optimize now if they might want to redo it in a year? And some software just rarely gets updated and will be legacy software that the thread director just has to guess at.
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You are right, the way it is worded...
It says:
"If Intel reaches 1,000 unit wafer output per month"
Which I was reading as it is below 1,000 about to reach 1,000. But the sentence could really mean anything.
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I'm fairly certain that any work optimizing for heterogeneous architectures will at least partially transfer to AMD's processors whenever they adopt this approach. Much of it is done through an abstraction layer and you're interacting with windows scheduling.
Send/receive is a constant but intermittent function. It lays dormant in the background until a set timer or internal hard coded one fetches or seeks a change in mail status on the target server.
I agree with the rest of what you've said though with intel's internal urge to add more e cores as they see fit those e cores should be able to be flexed to do what p cores can do but in the background. I said this last week but I think intel may have bitten off more than they can chew with how they developed their design.
AMD's approach is more sensible. It's a compact version of the same big core with less cache, and still includes smt. They're not like intel trying to juggle two different architectures with one not having ht/smt and now allegedly looking to ax ht/smt to solve their dilemma. this is like taking a power grinder to your scalp because you've got an itch there.
It probably is better overall, it basically lets them forego the development of their own ThreadDirector. The point I made originally still stands since from a development standpoint most of the work would carry over because the Windows OS will handle it through their own scheduling.
adroc_thurston
Diamond Member
- Jul 2, 2023
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Intel didn't need that either.
All the HMP scheduling work was done by MS for Qualcomm back in 2017.
Intel claims next-gen Xeon will have massive perf/watt improvements:
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