Discussion Intel current and future Lakes & Rapids thread

[mikk]

Pretty sure we will never see ADM on any of Intels GT2 SKUs for MTL and ARL. If there is a GT3 for ARL with 320EU or even 384EUs this could be an option. In the older ARL-P roadmap it sounded like ADM will be exclusive to GT3 models to maximize performance (GT3 N3 with ADM to maximize performance). ARL GT2 with 192EUs I don't think we will see this.

 

[A///]

I'd prefer to see av1 ancoding on inel gt before any of this tbh

 

[lightisgood]

Intel 17th Gen CPUs to Get Rentable Units: Why Hyper-Threading is Going Away | Hardware Times

Intel’s adoption of the hybrid core architecture has significantly changed the roadmap of the PC chipmaking industry. More and more applications are now taking advantage of the “secondary” low-power E-cores to boost performance and efficiency. This approach has its shortcomings, which Intel...

www.hardwaretimes.com

Intel is going to dynamic thread splitting...
I guess that the Slipstreame 2.0 will come, because E-core is best choice for speculative precomputation.

https://ericrotenberg.wordpress.ncsu.edu/files/2022/08/conference_ISCA-47-2.pdf

 

[DrMrLordX]

What was softmachines concept ?

@Geddagod beat me to it. Read his link. "Rentable units" seems like a retread of that.

 

[mikk]

I'd prefer to see av1 ancoding on inel gt before any of this tbh

Meteor Lake supports AV1 encoding, it's a newer media version of Arc Alchemist. It's a standalone lower clocked Media GT with 2x decode units and 2x encode units.

 

[igor_kavinski]

Intel is going to dynamic thread splitting...

Very interesting concept. SMT on steroids if they can somehow reduce P-core to E-core communication latency to bare minimum.

Why the term "rentable unit" for it, though?

 

[naukkis]

Intel 17th Gen CPUs to Get Rentable Units: Why Hyper-Threading is Going Away | Hardware Times

Intel’s adoption of the hybrid core architecture has significantly changed the roadmap of the PC chipmaking industry. More and more applications are now taking advantage of the “secondary” low-power E-cores to boost performance and efficiency. This approach has its shortcomings, which Intel...

www.hardwaretimes.com

Intel is going to dynamic thread splitting...
I guess that the Slipstreame 2.0 will come, because E-core is best choice for speculative precomputation.

Running speculative thread on E-core would not benefit anything. Speculative thread needs to be run ahead of main thread - so it need to be faster than main thread and so close to main thread that it will be part of cpu core to offer any meaningful help to execution.

 

[SiliconFly]

My bad. I think i didn't explain myself clearly.

(I was just comparing Zen 4 -> Zen 5 vs RPL -> ARL. Thats all)

What I was trying to say was, AMD is going from Zen 4 to Zen 5 (say N4 to N4P), and the density increase is non-existent. So, the transistor budget remains the same. The only way to increase IPC is to re-architect with the same amount of transistors (assuming the die size remains the same).

And Intel is going from RPL to ARL (say Intel 7 to 20A), the density increase is from 100 MTr/mm2 to around 300+ MTr/mm2. ARL gets 3X the transistors for the same die area.

Intel can shrink the ARL die to save cost, but I don't think they'll do that. I think the ARL die is gonna get a significantly higher transistor budget compared to RPL, And those excess transistors can easily be used to increase L2/L3 caches in the cpu tile or even increase core logic for more performance.

At least I was spot on about this a while back...

I did say ARL is gonna get a bigger cache. News leaks suggest that ARL is getting a 50% bump in L2. i.e, up to 3MB of L2.

Looks like, instead of doing something great with the massive transistor budget, Intel has chosen the easiest & safest way instead. Yuck.

 

[igor_kavinski]

Looks like, instead of doing something great with the massive transistor budget, Intel has chosen the easiest & safest way instead. Yuck.

Yeah coz that will mainly translate to better gaming performance and that's what they prefer to focus on. They have been failing at competing in MT workloads for a while now (barely stand up to 5950X and 7950X).

 

[Geddagod]

I did say ARL is gonna get a bigger cache. News leaks suggest that ARL is getting a 50% bump in L3. i.e, up to 3MB of L3.

Leak was talking about L2 not L3.

Looks like, instead of doing something great with the massive transistor budget, Intel has chosen the easiest & safest way instead. Yuck.

Why can't it be both?

Yeah coz that will mainly translate to better gaming performance and that's what they prefer to focus on.

Eh. Doubt they 'prefer' to focus on gaming performance.

They have been failing at competing in MT workloads for a while now (barely stand up to 5950X and 7950X).

?

 

[igor_kavinski]

?

Intel Core i9-13900KS mit 6,0 GHz im Test

Der Core i9-13900KS ist der erste Intel-Prozessor mit bis zu 6,0 GHz ab Werk. Die dritte Special Edition in Anwendungen und Spielen im Test.

www-computerbase-de.translate.goog

Even their KS paired with faster memory has trouble matching a 7950X in overall MT perf.

 

[SiliconFly]

Leak was talking about L2 not L3.

Oops. fixed

 

[SiliconFly]

Yeah coz that will mainly translate to better gaming performance and that's what they prefer to focus on. They have been failing at competing in MT workloads for a while now (barely stand up to 5950X and 7950X).

Definitely has a positive effect on gaming. But otherwise,.. meh.

 

[SiliconFly]

Why can't it be both?

I don't think it can be. Some leaks suggest ARL has RWC+ cores. Others suggest it has the first iteration of the LNC cores (and hence no hyper-threading).

If ARL has RWC+ cores, then there's nothing new to expect, except bigger caches and some minor improvements I guess.

If it has some form of LNC, then it's a whole different story. Need more clarity about ARL cores though.

 

[H433x0n]

Intel Core i9-13900KS mit 6,0 GHz im Test

Der Core i9-13900KS ist der erste Intel-Prozessor mit bis zu 6,0 GHz ab Werk. Die dritte Special Edition in Anwendungen und Spielen im Test.

www-computerbase-de.translate.goog

View attachment 84509
Even their KS paired with faster memory has trouble matching a 7950X in overall MT perf.

The benchmark you linked shows a single percentage point difference. I wouldn't consider that having trouble matching 7950X MT performance.

Just to save us time... Yes - I know it isn't anywhere near as efficient.

 

[Geddagod]

I don't think it can be. Some leaks suggest ARL has RWC+ cores.

Lol

Need more clarity about ARL cores though.

No. Only person who thinks it's RWC+ is witeken...

 

[A///]

Isn't he the hardcore intel apologist? can someone explain rentable cores to me.

 

[igor_kavinski]

Isn't he the hardcore intel apologist? can someone explain rentable cores to me.

From what I understand, Intel will slice a single thread into different instruction streams and try to process them on different cores so that if one instruction stream comes to a halt for whatever reason, the processing keeps going on, on the other cores and results are ready before the execution reaches that part of the process's instructions.

 

[igor_kavinski]

The benchmark you linked shows a single percentage point difference. I wouldn't consider that having trouble matching 7950X MT performance.

You are ignoring the fact that it takes a lot more effort to prevent the 13900KS from throttling. Similarly, the 5950X trumps the 12900KS.

 

[Saylick]

From what I understand, Intel will slice a single thread into different instruction streams and try to process them on different cores so that if one instruction stream comes to a halt for whatever reason, the processing keeps going on, on the other cores and results are ready before the execution reaches that part of the process's instructions.

That makes sense on paper but I'm not sure that's how it works in real life. I'm just an arm chair CPU architect, but if a single thread could be simply chopped up into smaller, bite sized portions that can be executed in parallel, wouldn't a GPU be better at the task? Single threaded processes tend to have a crap load of dependencies, which is why they run best on CPUs to begin with. If portions of the instruction stream could be done in parallel, well that's where having a superscaler execution engine comes in.

 

[igor_kavinski]

That makes sense on paper but I'm not sure that's how it works in real life. I'm just an arm chair CPU architect, but if a single thread could be simply chopped up into smaller, bite sized portions that can be executed in parallel, wouldn't a GPU be better at the task?

You would need a GPU that understood x86, AKA LARRABEE!

 

[Abwx]

From what I understand, Intel will slice a single thread into different instruction streams and try to process them on different cores so that if one instruction stream comes to a halt for whatever reason, the processing keeps going on, on the other cores and results are ready before the execution reaches that part of the process's instructions.

Isnt it what a OoO uarch is supposed to do..?.

 

[A///]

From what I understand, Intel will slice a single thread into different instruction streams and try to process them on different cores so that if one instruction stream comes to a halt for whatever reason, the processing keeps going on, on the other cores and results are ready before the execution reaches that part of the process's instructions.

very similar to how download streams work. each connection within the main download will download a portion of the file, if one fails others take over and then decompress the download from cache.

this being intel and I need not explain some half baked ideas they've had. I'm not sure if it'll work out well or bad.

 

[igor_kavinski]

Isnt it what a OoO uarch is supposed to do..?.

That happens inside a single core. Rentable cores are supposedly going to take this a step further and allow the instructions of a single thread to be executed out of order on different cores.

 

[igor_kavinski]

this being intel and I need not explain some half baked ideas they've had. I'm not sure if it'll work out well or bad.

I can believe it if Intel Israel is behind this innovation. They seem to be the ones always rescuing Intel in their time of need.