Discussion Intel current and future Lakes & Rapids thread

[SiliconFly]

Yep.

Arrow Lake's LNC is probably the first iteration of Jim Keller's work at Intel. Lets hope Intel starts sharing info soon enough.

 

[A///]

don't think so not in its full entirety. jim left intel on his own accord after facing a brick wall dealing with intel engineers and executives. intel filled in the gaps, I'm not expecting much. intel's habitualness for hiring or promoting from within is what keeps causing them to fumble. bad practices aren't weeded out. imagine seeing a staff of intel engineers headbutting against keller, you know the razzmatazz guy who gave intel the ole finger and kick up the hiny during the k7 days , k8 days and then ryzen. yeah intel folks, be a tight wad to the guy who caused your company pain on three separate occasions and still is today!

 

[SiliconFly]

don't think so not in its full entirety. jim left intel on his own accord after facing a brick wall dealing with intel engineers and executives. intel filled in the gaps, I'm not expecting much.

Arrow Lake & Lunar Lake are BOTH powered by Lion Cove.

Jim Keller laid the foundation for the new architecture long back. He may not be around now, but the work was already underway when he left. Probably almost complete by now. He spent 3 years at AMD and completely revamped it. His two years at Intel is good enough to lay the foundation for a new architecture. While leaving, he did mention that his work at Intel was complete.

And his new architecture can't debut in Lunar Lake cos Arrow Lake & Lunar Lake share the same Lion Cove architecture. Just that, Lunar Lake may feature an updated version of Lion Cove (LNC+). Thats all.

Either the new architecture starts with Arrow Lake. Or only after Lunar Lake. Not in-between. I think its highly likely that the new uarch will makes its debut in Arrow Lake. And considering all the rumors about ARL not being able to implement hyper-threading or the new 4-way threading, it looks more and more likely that ARL is the one with the new uarch.

 

[A///]

Arrow Lake & Lunar Lake are BOTH powered by Lion Cove.

Jim Keller laid the foundation for the new architecture long back. He may not be around now, but the work was already underway when he left. Probably almost complete by now. He spent 3 years at AMD and completely revamped it. His two years at Intel is good enough to lay the foundation for a new architecture. While leaving, he did mention that his work at Intel was complete.

And his new architecture can't debut in Lunar Lake cos Arrow Lake & Lunar Lake share the same Lion Cove architecture. Just that, Lunar Lake may feature an updated version of Lion Cove (LNC+). Thats all.

Either the new architecture starts with Arrow Lake. Or only after Lunar Lake. Not in-between. I think its highly likely that the new uarch will makes its debut in Arrow Lake. And considering all the rumors about ARL not being able to implement hyper-threading or the new 4-way threading, it looks more and more likely that ARL is the one with the new uarch.

the rumor was at intel it was a daily struggle between him and brick walls trying to advance the company's designs. if his involvement in that cove uarch is used in arrow lake and arrow lake is is abysmal according to a few loud new members then it can be said his work at intel was fruitless.

 

[SiliconFly]

the rumor was at intel it was a daily struggle between him and brick walls trying to advance the company's designs. if his involvement in that cove uarch is used in arrow lake and arrow lake is is abysmal according to a few loud new members then it can be said his work at intel was fruitless.

Pat Gelsinger himself is no less a tech wiz when compared to Jim Keller. I'm pretty sure what keller started should be pretty much complete by now. Or even modified & updated. And it's waaayyyy too early for ARL performance projections. I'm pretty sure it's gonna be better than MTL. Just how much better is something we need to wait and watch.

 

[A///]

Pat Gelsinger himself is no less a tech wiz when compared to Jim Keller. I'm pretty sure what keller started should be pretty much complete by now. Or even modified & updated. And it's waaayyyy too early for ARL performance projections. I'm pretty sure it's gonna be better than MTL. Just how much better is something we need to wait and watch.

pat speaks to jesus, hand on heart. lol yeah you're saying here what I've been groaning about for two or three weeks now. people getting hard up on some dumb projections based on flimsy testing with unknown variables. intel finished up what jim started but we won't know much about arrow until around february of this coming year. if that wasn't obvious unless some of you have time travel machines!

 

[A///]

for you shadow players out there what ever stopped intel from doing what amd did by developing a denser core version of a core ark they had? do they not possess the skill or man power for this or did they think teaming normal core ark with the small core stuff based on atom would be a better idea or did they have a dumb moment and went with atom because they didn't imagine or think of doing a dense core?

 

[A///]

they're dropping smt?

 

[Henry swagger]

Yep.

Arrow Lake's LNC is probably the first iteration of Jim Keller's work at Intel. Lets hope Intel starts sharing info soon enough.

Aint lion cove gonna have 700+ robs and a 8 wide decode ? .. the core will be as wide as Apple's m2 core

 

[A///]

rops but yes that's what I believe to be true harry given some tweet of rochy's that was posted forever ago. there's a rumor of intel dropping smt for 32 individual threads like they are mimicking apple here. who knows what kind of crack cocaine they're using at intel. something ain't right with those people.

 

[igor_kavinski]

there's a rumor of intel dropping smt for 32 individual threads like they are mimicking apple here. who knows what kind of crack cocaine they're using at intel. something ain't right with those people.

Interested in your take on why losing SMT in favor of 32 threads is bad. I think they looked at the E-cores and went, hey, we don't need HT anymore. Let's have REAL threads forever!

 

[igor_kavinski]

None of this forces Intel to launch a desktop Meteor Lake chip. But it would certainly make a nice SFF PC, HTPC, or industrial PC even if it just just an H laptop chip put into a desktop socket.

Thank you for the commendable effort, Sir Dullard.

I'm beginning to see a picture.

Intel releases RPL-R to sell more CPUs to OEMs and also to entice enthusiasts and gamers to upgrade their by-now-stale 12th/13th gen CPUs.

At the same time, Intel needs to sell a platform (CPU+chipset) for even more moneeeehhhh so they squeeze out a stillborn MTL-S Core Ultra 5 on the 800 series chipset and show how it makes for a really nice budget gaming system without having to shell out the extra cash for a dGPU. Plus, the 800 series chipset will accept Arrow Lake so all those Core Ultra 5 owners can be converted into more CPU sales through upgrading.

It's a multi-pronged approach to turn a profit on as many fronts as they can. Kind of like punching and kicking Thanos from all directions in Avengers Infinity War, only the Thanos they are disorienting is the PC market. AMD as usual won't be able to grab more than 20% (very optimistic) share of new PC sales.

 

[A///]

Interested in your take on why losing SMT in favor of 32 threads is bad. I think they looked at the E-cores and went, hey, we don't need HT anymore. Let's have REAL threads forever!

smt on x86 provides around 18-23% improvement in performance. threads going up is not linear performance which is why all the idea of 4 way smt are bull crap. intel losing or dropping smt places more emphasis on the p and e cores to be performant each generation of processor family whether or not the cores architectures move onto a next one. the smt being present gives them a little breathing room. intel can drop smt if they can provide a reasonable ipc increase each generation, but that's not something they've been able to acocmplish. this tells me they feel dropping the ened for smt opens up space for a better core design or placing more e cores in there or p cores in future.

on the other hand dropping smt or ht for intel drops the physical logic units off the die, it reduces complexity and cost, and in turn will use anywhere from 10-22-25% less power under full load. you could laser fuse the logic units off so there's no active state when under load for the associated core but you're wasting space and increasing complexity and manufacturing costs if you can't get it right and need to heavily bin.

to me this is like intel trying to repliacate amd's compute dies. lowering costs to bare minimum but it's a weird formula.

 

[Henry swagger]

smt on x86 provides around 18-23% improvement in performance. threads going up is not linear performance which is why all the idea of 4 way smt are bull crap. intel losing or dropping smt places more emphasis on the p and e cores to be performant each generation of processor family whether or not the cores architectures move onto a next one. the smt being present gives them a little breathing room. intel can drop smt if they can provide a reasonable ipc increase each generation, but that's not something they've been able to acocmplish. this tells me they feel dropping the ened for smt opens up space for a better core design or placing more e cores in there or p cores in future.

on the other hand dropping smt or ht for intel drops the physical logic units off the die, it reduces complexity and cost, and in turn will use anywhere from 10-22-25% less power under full load. you could laser fuse the logic units off so there's no active state when under load for the associated core but you're wasting space and increasing complexity and manufacturing costs if you can't get it right and need to heavily bin.

to me this is like intel trying to repliacate amd's compute dies. lowering costs to bare minimum but it's a weird formula.

Wonder what are rentible units jim keller created for royal core in beast lake ? .. i think p and e cores fusing in to one super core for single thread dominance lol

 

[A///]

Wonder what are rentible units jim keller created for royal core in beast lake ? .. i think p and e cores fusing in to one super core for single thread dominance lol

I'm not familiar with the rentable units and it's been bothering me for about two months now since the rumor came out. the rumors add up with what intel planned on doing. ht/smt was a fix to a problem but that problem was over 20 years ago. idk if intel's e core only xeon is out but that might give you a basic idea of what performance might be like if you had more room and "power in the bank" to work with.

let's not forget that before controe came along an ugly girlfriend called pentium d did. could intel be onto the next big thing? who knows but it ain't looking like it anytime in the next 3 years.

If adroc is to be believed and he does make some wild claims, diy computing is going to get expensive with amd the only player in town who isn't as reserved as intel when it comes to pricing.

 

[JoeRambo]

on the other hand dropping smt or ht for intel drops the physical logic units off the die, it reduces complexity and cost, and in turn will use anywhere from 10-22-25% less power under full load. you could laser fuse the logic units off so there's no active state when under load for the associated core but you're wasting space and increasing complexity and manufacturing costs if you can't get it right and need to heavily bin.

I think the road for SMT is unclear in mobile/desktop computing. Does it make much sense for 8 + 32 CPU? let's say it provides 25% throughput and E cores are 66% of P perf. 10 + 21 vs 8 + 21 => is 10% IDEAL throughput increase.
The keyword being IDEAL, as real SoC will be thermals/power limited and will need to drop clocks in P and E clusters. So our theoreticals might not apply or even produce a negative scaling in some thermals restricted scenario, where P cores overheat.

Intel might have some interesting sharing for cores in mind. What are the main users of transistors? Caching structures, be it mem, branches or TLBs. It would be madness to share "L1" of those due to performance, but "L2" structures are really massive, multi ported structures that sit idle if
So Intel might have went to create "Penryn" like module of 2 cores, where each core has "L0" of 48KB, L1 of 256 and then L2 shared by 2 cores of some 6-8MBs and traditional L3 on SoC.
L2 TLBs are also shared and so is massive L2 BTB. is there huge L2 TLB that is also shared? Very much possible.

That is a sharing that increases performance in straightforward, energy saving way without blowing up transistor budgets / per core.

 

[A///]

ht/smt was a fix to a problem but that problem was over 20 years ago.

 

[Geddagod]

Chonk L2, also could make sense considering ARL is also rumored to add in an extra level of cache between the 3MB L2 and the L1. Cache hierarchy changes are always fun 🙂

 

[A///]

View attachment 84344
Chonk L2, also could make sense considering ARL is also rumored to add in an extra level of cache between the 3MB L2 and the L1. Cache hierarchy changes are always fun 🙂

wasn't too long ago people thought the cache change was for a larger l3 or a new l4 cache, or the adamamajama whatever exist was huffing about.

 

[SiliconFly]

wasn't too long ago people thought the cache change was for a larger l3 or a new l4 cache, or the adamamajama whatever exist was huffing about.

I'm pretty sure MTL features some form of ADM L4. At least some specific parts as it's not cheap. And it'll be part of the active interposer base tile as shown in a Intel slide. Probably a few 100 MBs.

 

[A///]

I'm pretty sure MTL features some form of ADM L4. At least some specific parts as it's not cheap. And it'll be part of the active interposer base tile as shown in a Intel slide. Probably a few 100 MBs.

whoops, yes it appears it was for mtl and not arl. I had it written down for arl. might be a mobile soc feature only going forward to get the best bang out of the processor in a limited thermal and power envelope. but with intel the envelope is a 20 x 20 foot wooden crate.

 

[DrMrLordX]

Wonder what are rentible units jim keller created for royal core in beast lake ? .. i think p and e cores fusing in to one super core for single thread dominance lol

Intel bought out Softmachines years ago, and all signs point to their efforts being dead. It seems unlikely they'll resurrect the concept.

idk if intel's e core only xeon is out

If you are referring to Sierra Forest, no. It is supposed to launch in Q2 2024.

 

[Henry swagger]

Intel bought out Softmachines years ago, and all signs point to their efforts being dead. It seems unlikely they'll resurrect the concept.



If you are referring to Sierra Forest, no. It is supposed to launch in Q2 2024.

What was softmachines concept ?

 

[Henry swagger]

Weiterleitungshinweis

I know what rentable units are now.. jim keller is fusing p core together in groups gpu like for incredible ipc.. cougar cove is royal core

 

[Geddagod]

I'm pretty sure MTL features some form of ADM L4. At least some specific parts as it's not cheap.

Apparently it's been canned very early in MTL's design cycle. Wouldn't expect it at all tbh.

And it'll be part of the active interposer base tile as shown in a Intel slide. Probably a few 100 MBs.

C&C article off of Intel's Hotchips 34 presentation refers to the base tile as passive.

What was softmachines concept ?

Here's Anandtech's article on it

I know what rentable units are now.. jim keller is fusing p core together in groups gpu like for incredible ipc.. cougar cove is royal core

If that exists, and if that's what Royal Cove is indeed, then it's likely you won't see that until after Panther Lake, according to Raichu. MLID is the one trying to convince everyone that LNC is royal core, and as ARL got closer and closer, he is now insisting that LNC in ARL isn't royal core (with RU) but LNC+ in Diamond Rapids and Lunar Lake is going to be. Rolls eyes.