Discussion Intel current and future Lakes & Rapids thread

[H433x0n]

Intel 4 was in development for a very long time even before pat gelsinger joined & considering MTL ES samples are comfortably hitting 5GHz+, I'd say Intel 4 is in fact a very healthy state. Might meet all targets. No doubt.

But the same doesn't apply to Intel 20A. Max clock regression (Fmax) is still very much an big question with Intel 20A. And yields too. Worst part is, we're already in Q3 2023 and Intel still hasn't announced ARL 20A tapeout yet which is pretty serious. At this point, ARL might not make it out in 2024!

We’re still a year out from when 20A would hit high volume manufacturing for the select ARL dies that will be manufactured internally. I don’t think it’s time to begin panicking yet.

According to the VLSI symposium PowerVia is progressing on schedule. This was viewed as one of the bigger challenges of the 20A/18A process. So from the publicly available information ~half of the process tech seems okay.

 

[ondma]

From a reply (emphasis mine):

RWT Forums - Real World Tech

content overridden

www.realworldtech.com

It might just as well be a quess (and more decode capability for Zen 5 is to some degree "for granted" anyway) but still fun to point out

I'm still holding on to my dream that AMD set up similar targets for Zen 5 as they did for Zen 1:

• ~40% ST IPC uplift with slightly regressed (<10%) clocks for top-end desktop (gettin full worth of the IPC in server and mobile)
• 8 wide decode (possibly Tremont style 4+4)
• a much large ROB, wider backend, all the other goodies ...

And that they'll then continue to expand that same core architecture for 3-4 major iterations (as with Zen 1)

Ambitious? Yes, very much so , but so was Zen. And as we know "only the paranoid survive". If Intel continued to execute with Arrow Lake as they did with Tiger Lake and Alder Lake, it would be pretty much the minimum required just to keep a slight edge. And it's not smart to make business plans on the assumption of the competitor to screwing up forever. That leads to where AMD was in 2006 Or Intel in 2017.

Those seem very optimistic targets. The 40% uplift for Zen 1 was relatively easy, coming from a very poor Bulldozer architecture. It is a much higher bar to get a similar uplift over Zen 4. "Luckily" for AMD, with all the rumors and uncertainly surrounding ARL, even a more realistic 20% or so should put them comfortably in the lead in most applications.

 

[Exist50]

This morning I indirectly stumbled upon Linus Torvalds' opinion on the matter. Bold emphasis mine.

I think it's worth mentioning that Linus is speaking in the context of a kernel dev. Software that already uses AVX512 should have a very smooth transition to AVX10. The Adobe suite will probably be ready day 1. APX is probably a bigger hurdle from an ecosystem perspective.

 

[A///]

Oh, in case I wasn't clear then, that chip they were showing off was the Intel 4 "custom networking ASIC" that's popped up on slides. Doubt we'll see any silicon from this new deal for a while yet. For these kind of contracts, serious work only begins after the deal is won.

Ah and the mystery is solved. Ericsson. They did cross my mind but I didn't think they were doing anything cool these days when I asked you.

 

[A///]

and like that the bull rumors of increased prices were just that, bs. no idea why people eat this crap up as if it's gods words to consumers ears.

 

[Saylick]

and like that the bull rumors of increased prices were just that, bs. no idea why people eat this crap up as if it's gods words to consumers ears.

The same people peddling the rumors are also the same people announcing they were BS. If they write it, people will read it, eyeballs means clicks and impressions, and those means ad money. Imo, you can't just blame the consumer.

 

[Exist50]

Ah and the mystery is solved. Ericsson. They did cross my mind but I didn't think they were doing anything cool these days when I asked you.

Ah, didn't realize you missed me mentioning that a while back. I don't think they're particularly secretive about these things either. It's just that no one looks too deeply into 5G base-station hardware. Plenty of interesting stuff from Marvell too, but people care even less about them, which is a shame.

From everything I hear, that team is one of Intel's least dysfunctional. High praise, I know. They even bailed out Granite Rapids for a while.

 

[A///]

The same people peddling the rumors are also the same people announcing they were BS. If they write it, people will read it, eyeballs means clicks and impressions, and those means ad money. Imo, you can't just blame the consumer.

and then the masses give them the finger and tell them other not so kind words, and next week it's a wash and rinse of everything. people still listen to dummies like mlid whose mother likely conceived him while being a wino and he'll delete his bs or make up any excuses that he was technically right. don't get me started on the dime store version of the gamers nexus guy with the irritatingly gordon elliot knockoff voice.

 

[A///]

Ah, didn't realize you missed me mentioning that a while back. I don't think they're particularly secretive about these things either. It's just that no one looks too deeply into 5G base-station hardware. Plenty of interesting stuff from Marvell too, but people care even less about them, which is a shame.

From everything I hear, that team is one of Intel's least dysfunctional. High praise, I know. They even bailed out Granite Rapids for a while.

if we're referring to that image of the hand holding a mcm, yeah that is what I was wasking you about a few weeks ago and you played a game during a time of despair for me, that being me being several glasses in for the night and thinking I could think.

 

[Exist50]

if we're referring to that image of the hand holding a mcm, yeah that is what I was wasking you about a few weeks ago and you played a game during a time of despair for me, that being me being several glasses in for the night and thinking I could think.

Ah, yup. Must have been asleep when I eventually coughed up the answer. Anyway, yeah, that chip is for Ericsson. Must be doing ok, if they're willing to go back to Intel for the next gen.

 

[Gideon]

Those seem very optimistic targets. The 40% uplift for Zen 1 was relatively easy, coming from a very poor Bulldozer architecture. It is a much higher bar to get a similar uplift over Zen 4. "Luckily" for AMD, with all the rumors and uncertainly surrounding ARL, even a more realistic 20% or so should put them comfortably in the lead in most applications.

Yes, but Zen 1 also widened the core massively, essentially "doubling up" everything and it ended up with over a 50% IPC uplift (not including SMT).

Zen 3 on the other hand managed +20% IPC while not widening the core at all. All of that on the same node with a 10% growth in size. With that perspective I would consider getting 20% more IPC from a lot wider design to be a relatively mediocre achievement.

In the end it all depends how much silicon they throw at the problem (and how good they are at it)

Designing a core with 30-40% more IPC is very possible when the essentially double the width again (not saying they will do it, but in principle). The hard part is to not "explode" the transistor budget, keep the size and clocks in check. Otherwise it might end up like the late Samsung cores. That were much wider than the predecessors, but also drew a ton of power and ended up no faster - while wasting a whole lot of transistors for that privilege.

Make no mistake, designing a good 2x wider core is a very hard problem. I'd say, it's an order of magnitude more complex task. But if it's done well, a 40% uplift is most certainly possible.

Let's not forget that nearly a decade has passed since the mid 2010'ies when Zen 1 was designed (with considerable improvements in available compute power and algorithms).

And while AMD has iterated a lot on Zen 1, they even changed many of the underlying "lego blocks" in Zen 3, they kept the overall design still surprisingly close to the original:

Zen 1

vs Zen 4

It would only make sense to redesign the architecture fundamentally once more - to again have 2-3 generations of low-risk fine-tuning iterations (Zen 6, Zen 7 ...).

Not doing it is certainly less risky (and cheaper) but also reaps less rewards.

Just my 2 cents.

 

[dullard]

Yes, but Zen 1 also widened the core massively, essentially "doubling up" everything and it ended up with over a 50% IPC uplift (not including SMT).

Zen 1
...

vs Zen 4

Please keep this level of Zen detail in the AMD thread.

 

[lightisgood]

Isn't Qualcom in the RAMP-C Program of Intel?

RAMP-C Program on Intel 18A Adds 2 Strategic Defense Industrial Base Customers

www.intel.com

"Boeing and Northrop Grumman join the current lineup of RAMP-C customers – Nvidia, Qualcomm, Microsoft and IBM – and will work closely with Intel and its ecosystem partners, Cadence and Synopsys, to enable access to state-of-the-art technologies that help protect U.S. national security.
The program allows both commercial foundry customers and the DoD to utilize Intel’s significant investments in leading-edge process technologies, including Intel 18A, and establishes an ecosystem for commercial and government customers. Intel 18A process development continues on track and RAMP-C customers are developing test chips."

Or is the RAMP-C different?

Yes. Qualcomm is RAMP-C customer, however, it doesn't mean Qualcomm is huge IFS customer.
Also NVIDIA isn't yet huge IFS customer too.

Nvidia in Talks to Use Intel as a Foundry to Manufacture Chips

CEO Jensen Huang is open to Intel making Nvidia's chips

www.tomshardware.com

"Foundry discussions take a long time, and it's not just about desire. We have to align technology, the business models have to be aligned, the capacity has to be aligned, the operations process and the nature of the two companies have to be aligned. It takes a fair amount of time and a lot of deep, deep discussion – we're not buying milk here. This is really about the integration of the supply chains. Our partnerships with TSMC and Samsung in the last several years are something that took years to cultivate. So we are very open-minded to considering Intel, and I'm delighted by the efforts that they're making."

 

[aigomorla]

Talking about Zen in Intel thread when it comes to a point to point comparison is fine. For example, your talking registers, or FAB comparisions, but I better see the words INTEL in that post as you are pointing to a comparsion of some form.

Giving me a history of ZEN in an intel Thread is ABSOLUTELY not allowed, as that is not what we are talking about, unless you are comparing the progression side by side with INTEL, and again, it BETTER have the words INTEL in that post.

Do it again, and you will be given Infractions.

Moderator Aigo

 

[Geddagod]

Intel once again reiterates that Arrow Lake will use 20A, in their q2 earnings call. Seems like they will have some 20A skus, even if others are cancelled

 

[mikk]

Meteor Lake PRQ in Q3, Arrow Lake first stepping running in the lab.

 

[SiliconFly]

It would only make sense to redesign the architecture fundamentally once more - to again have 2-3 generations of low-risk fine-tuning iterations (Zen 6, Zen 7 ...).

Not doing it is certainly less risky (and cheaper) but also reaps less rewards.

Just my 2 cents.

Not sure who the user is, but kindly requesting the mods to excuse this one time. Might have been a simple oversight.

On the topic of new architectures, it's usually extremely difficult. A new arch takes many years to develop & is very very expensive. And the outcome is also not always guaranteed. It may shine in simulations, but stumble in real world. Like bulldozer. An expensive mistake that almost killed AMD.

Intel on the other hand is slowly switching to a new architecture in carefully orchestrated steps, that is, incrementally shifting to a new arch with fallbacks. Typical Intel modus operandi.

First, total dis-aggregation with MTL (same core but tons of new tech)
Then, ARL with BPD & GAA & some IPC improvements (Fallback: If they screw-up ARL, we'll get a MTL refresh)
Then, LNL with new P-cores & improved E-cores (Fallback: If they screw-up LNL, we'll get a ARL refresh)
Then, something about extreme dis-aggregation & high IPC gains.

Remember, Keller joined Intel in 2018 to come up with a new architecture. And the first iteration (LNL) is coming out only in 2025. Thats a total of 7 years!

I'd say a minimum of 5 years is required for developing a new architecture from scratch to actual manufacturing.

 

[SiliconFly]

Intel once again reiterates that Arrow Lake will use 20A, in their q2 earnings call. Seems like they will have some 20A skus, even if others are cancelled

It'll be real impressive if Intel can actually pull-off ARL on 20A on time. Even though they mentioned in their Q2 earnings call that 3, 20A & 18A are well on track, a ARL tapeout on 20A is still pending this late in the cycle. They should have achieved power-on by now, if ARL has to make it to market by late 2024.

 

[mikk]

It'll be real impressive if Intel can actually pull-off ARL on 20A on time. Even though they mentioned in their Q2 earnings call that 3, 20A & 18A are well on track, a ARL tapeout on 20A is still pending this late in the cycle. They should have achieved power-on by now, if ARL has to make it to market by late 2024.

First ARL stepping is running in the lab, although we don't know what node it is running on. Considering they even have 18A test chips taped out they should have 20A as well.

 

[SiliconFly]

First ARL stepping is running in the lab, although we don't know what node it is running on. Considering they even have 18A test chips taped out they should have 20A as well.

Actually, I'd like to clarify. 20A & 18A tapeouts have happened already. They're just reference (industry standard) cores. More a proof of concept rather than a real product.

But ARL tapeout hasn't happened or been announced yet.There's actually no real information yet on an actual ARL tapeout or any stepping running in a lab! But I wish it were true.

 

[mikk]

But ARL tapeout hasn't happened or been announced yet.There's actually no real information yet on an actual ARL tapeout or any stepping running in a lab! But I wish it were true.

Gelsinger told ARL is running in the lab with the first stepping, of course it taped out.

 

[mikk]

Actually he told "On Intel 20A Arrow Lake volume client product is currently running its first stepping in the fab"

To me it means it's running on 20A. Even Lunar Lake taped out over half a year ago. They don't publish tape outs for every chip, actually it's very rare.

 

[Geddagod]

Actually he told "On Intel 20A Arrow Lake volume client product is currently running its first stepping in the fab"

To me it means it's running on 20A. Even Lunar Lake taped out over half a year ago. They don't publish tape outs for every chip, actually it's very rare.

Intel has started being way more transparent with major milestones. Starting with MTL IIRC. They announced a lot of MTL milestones, and talked about so far, ARL milestone (today), LNL, GNR (first stepping out of the fab), and would have shared a SRF die shot early if the guys over at Intel could organize their wafers...
conspiracy theory Intel didn't have a SRF wafer ready so they just grabbed a SPR one and claim they made a mistake

 

[SiliconFly]

Actually he told "On Intel 20A Arrow Lake volume client product is currently running its first stepping in the fab"

To me it means it's running on 20A. Even Lunar Lake taped out over half a year ago. They don't publish tape outs for every chip, actually it's very rare.

This is what CEO Pat Gelsinger actually said on feb 24th:
“The simple answer is no. No delays. Arrow Lake is on track. The 3nm programs are on track, both with TSMC as well as our internal 3nm programs including Granite Rapids and Sierra Forest.”

Nothing specific about ARL tapeout or Power-on or first stepping or ES. Just said it's on track.

They don't need to publish, but information leaks happen almost always.

 

[SiliconFly]

Intel has started being way more transparent with major milestones. Starting with MTL IIRC. They announced a lot of MTL milestones, and talked about so far, ARL milestone (today), LNL, GNR (first stepping out of the fab), and would have shared a SRF die shot early if the guys over at Intel could organize their wafers...
conspiracy theory Intel didn't have a SRF wafer ready so they just grabbed a SPR one and claim they made a mistake

Today? awesome. Will check it out.