Discussion Intel current and future Lakes & Rapids thread

[nicalandia]

I'm pretty sure I've warned people on AT Forums several times already on rumours regarding Zen 5, I'm not going to be doing it again.

They will put 128 Cores on 8 chiplets for Bergamo, they have the space to put at least 192 Cores on 12 chiplets on the same package so.....

 

[inf64]

I'm pretty sure I've warned people on AT Forums several times already on rumours regarding Zen 5, I'm not going to be doing it again.

So there will be no increase in core count with Zen5? Ok fine, let me ask another question: will intel have 128 big cores in 2024?

 

[uzzi38]

So there will be no increase in core count with Zen5? Ok fine, let me ask another question: will intel have 128 big cores in 2024?

I love how the only options are double or nothing.

 

[igor_kavinski]

will intel have 128 big cores in 2024?

Maybe the largest ever monolithic CPU with sub-Ghz speeds if they really try.

 

[uzzi38]

They will put 128 Cores on 8 chiplets for Bergamo, they have the space to put at least 192 Cores on 12 chiplets on the same package so.....

I really hope you're not equating Zen4C to Zen5.

 

[inf64]

I love how the only options are double or nothing.

I think you underestimate the deficit intel will have in server market. Sure, AMD may screw up and run into unforeseen problems, but intel has been delaying so many products for so long that I have no idea how they will compete in 2024.

 

[uzzi38]

I think you underestimate the deficit intel will have in server market. Sure, AMD may screw up and run into unforeseen problems, but intel has been delaying so many products for so long that I have no idea how they will compete in 2024.

I think you're putting too much stock into the rumours suggested by people that have been consistently wrong. That's the point I'm trying to make here. I'm not even suggesting that AMD have screwed up or anything. Lets just take a couple of steps back and look at what the people claiming 192/256 cores have been saying over the last year:

1. Zen 4 IPC claims - most of the claims were dead wrong from the beginning.

2. RDNA3 claims - FP32 numbers taken wildly out of context to try and imply we'd be seeing 2.5x+ gaming performance gains.

Why are you going to take them seriously when they make the claim that Zen 5 will literally double core count on the same platform?

 

[inf64]

I think you're putting too much stock into the rumours suggested by people that have been consistently wrong. That's the point I'm trying to make here. I'm not even suggesting that AMD have screwed up or anything. Lets just take a couple of steps back and look at what the people claiming 192/256 cores have been saying over the last year:

1. Zen 4 IPC claims - most of the claims were dead wrong from the beginning.

2. RDNA3 claims - FP32 numbers taken wildly out of context to try and imply we'd be seeing 2.5x+ gaming performance gains.

Why are you going to take them seriously when they make the claim that Zen 5 will literally double core count on the same platform?

I get what you are saying, but can you answer my question? Let's assume AMD has "only" Genoa-X 96C and Bergamo Zen4c with 128 cores. What will intel's answer be in 2024?
What do you expect their stack to look like and how can they be competitive again?

 

[igor_kavinski]

How about a hybrid dual socket system from Intel? 56 P-cores in one socket and 128 E-cores in the other one, each with their own dedicated memory. Server applications will have to be configured for affinity to whatever core types they take the best advantage of.

 

[eek2121]

If I were still in IT and responsible for buying server hardware, I would absolutely NOT be buying Intel right now. I can't imagine my sentiment is unique. Hopefully sales will bleed enough for them to fix whatever issues are causing the delays and start getting Xeons out the door.

I think you're putting too much stock into the rumours suggested by people that have been consistently wrong. That's the point I'm trying to make here. I'm not even suggesting that AMD have screwed up or anything. Lets just take a couple of steps back and look at what the people claiming 192/256 cores have been saying over the last year:

1. Zen 4 IPC claims - most of the claims were dead wrong from the beginning.

2. RDNA3 claims - FP32 numbers taken wildly out of context to try and imply we'd be seeing 2.5x+ gaming performance gains.

Why are you going to take them seriously when they make the claim that Zen 5 will literally double core count on the same platform?

Maybe they will have quad sockets, or SMT4 (/s in case it's needed )

 

[igor_kavinski]

If I were still in IT and responsible for buying server hardware, I would absolutely NOT be buying Intel right now.

Good luck trying to find AMD server hardware. At least where I live (U.A.E.), asking for AMD is met with blank stares. Even the Azure data centers here have only one Epyc based HBv2 series available with no option other than 120 cores.

 

[ashFTW]

Will intel have 256 cores in server SKUs? That's what it takes to be competitive with Zen5. I somehow doubt it, but who knows.

Sierra Forest (SF) coming in 2024 along with Granite Rapids (GR) on the same Eagle Stream platform should have 3-4 times more cores than GR, based on area alone. I expect GR to be at least 128. I have speculated on this before. Whether it’s competitive with Zen 5, I do think so, but only time will tell. The way Intel server group is executing, one has to be quite skeptical.

I expect GR, SF, and Falcon Ridge to all be 4 stack Foveros, and share the base tiles where all the I/O, memory, and cache will be. Note that Ponte Vecchio and Rialto Bridge are both 2-stack designs.

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Edit: Fixed some typos.

 

[igor_kavinski]

Sierra Rapids (SR) coming in 2024 along with Granite Rapids (GR) on the same Eagle Stream platform should have 3-4 times more cores than GR.

Intel Sierra Forest the E-Core Xeon Intel Needs

We discuss the Intel Sierra Forest announcement at Intel Investor Meeting 2022. This is the high E-core count chip Intel needs

www.servethehome.com

Sierra Forest in that slide.

 

[ashFTW]

Intel Sierra Forest the E-Core Xeon Intel Needs

We discuss the Intel Sierra Forest announcement at Intel Investor Meeting 2022. This is the high E-core count chip Intel needs

www.servethehome.com

Sierra Forest in that slide.

Thanks! I fixed the typo. I’ll update the figures later today.

 

[nicalandia]

Thanks! I fixed the typo. I’ll update the figures later today.

Theoretically speaking, Intel could fit 240+ cores(60+ per tile) on a Sapphire Rapids size CPU, how much more IPC can they extract from such efficient design is to be seen(Gracemont IPC is about on par with Skylake, will those Crestmont cores be on par with Ice Lake?

 

[ashFTW]

Theoretically speaking, Intel could fit 240+ cores(60+ per tile) on a Sapphire Rapids size CPU, how much more IPC can they extract from such efficient design is to be seen(Gracemont IPC is about on par with Skylake, will those Crestmont cores be on par with Ice Lake?

Roughly 3-4 Gracemont cores can fit inside a Goldencove core. I assume you multiplied the 15 cores on Sapphire Rapids (SPR) tile by 4 to reach 60?

The SPR tile has a ton of uncore stuff (PCIe, UPI, HBM and DDR5 controllers, inter tile fabric etc) that won’t be needed in the disaggregated Granite Rapids (GR) and Sierra Forest (SF) designs. These IP blocks (except some Foveros chiplet interconnect) will move to the base tile, leaving a lot more space on the top tile for cores. Additionally, the Intel 3 process will provide much needed density improvements (~1.6x? compared to Intel 7). Each GR tile could easily fit 32 P-cores, and still be smaller. Thats how I conservatively reached the 128 number of total p-cores. Using the above E-cores per P-core multiplier, conservatively 96 E-cores can be put on the similar sized tile for a total of 384 E-cores for 4 tile SF. It could even be 128 E-cores per tile, if a denser Intel 3 library is used, since very high frequencies are not required for SF SKUs.

Edit: The uncore takes up a whopping 50% of the Sapphire Rapids XCC tile, even though it only has 1/4th the I/O and memory support.

.

 

[IntelUser2000]

I don't think it'll quadruple Granite Rapids core count. It might double it at best for lower cost and better power efficiency for cloud workloads.

@ashFTW Falcon Shores features "anstrom era process", so 20A is a good expectation.

Also the roadmap seems to point to coming in 2024 like with Granite Rapids?

So there will be no increase in core count with Zen5? Ok fine, let me ask another question: will intel have 128 big cores in 2024?

There's the earlier GNR slide that suggested two compute tiles with 60 cores each. Don't know how literally we can take that though.

@uzzi38 What you are saying kinda makes sense. If it's on 5nm then it's the same node. If Zen 5 core is a big uarch gain. Maybe something like 160 cores?

 

[ashFTW]

I don't think it'll quadruple Granite Rapids core count. It might double it at best for lower cost and better power efficiency for cloud workloads.

We know that Granite Rapids and Sierra Forest are on the same platform and that they are disaggregated. The platform capabilities will be derived from the base Foveros tiles. To be competitive, it will be a “4-stack” Foveros design, which will allow for a large “Rambo” cache as well. Each of the top 4 tiles (or groups of subtiles) will be approx 500 mm2. Lets assume 20% of this area will be lost to Foveros power delivery and tile interconnect. One important thing to keep in mind is that these will be made on Intel 3, so we will get 1.5x or so density improvement wrt Intel 7.

Granite Rapids: So how many P-cores can one fit in 600mm2 (400x1.5) on Intel 7? 15 Golden cores take 200mm2, or 13.3mm2 per core. Lets make the new core size 15mm2 to account for new features. The answer is 40 P-cores per tile, or 160 cores per chip with 4 top tiles. I watered down this number to 128. Of course power will be a big gating factor. The TDP of these chips might top 500/600W.

Sierra Forest: Assuming 3 E-cores per P-core, we get 384 max E-cores. This number could be higher, even as high as 512, if a denser and more power efficient version of the Intel 3 process is used instead.

Now, how these tiles are packaged in SKUs is of course a business decision based on customer needs, competitive landscape, and yields. Unlike Sapphire Rapids, there is no longer a need to always include 4 tiles to get the full platform capability. Using just 2 E-core tiles might reach close to 256 cores, arriving at your likely configuration. The beautiful thing is that these are late binding decisions, that rely solely on backend packaging processes.

Falcon Shores features "anstrom era process", so 20A is a good expectation.

The base tiles that have all the I/O may stay with Intel 3; Intel 20A may again be just like Intel 4, and only have high performance libraries. Subtiles of the Xe tile maybe made with 20A and external sources. The x86 core tiles will likely stay as-is on Intel 3 for the first Falcon Shores release. The next Falcon Ridge release could be based on Diamond Rapids and whatever the next E+core is. Once there is a stable platform with well defined chiplet interfaces, there is a lot of flexibility.

 

[IntelUser2000]

Sierra Forest: Assuming 3 E-cores per P-core, we get 384 max E-cores. This number could be more if a denser and more power efficient version of the Intel 3 process is used instead; even as high as 512.

How these tiles are packaged in SKUs is of course a business decision. Unlike Sapphire Rapids, there is no longer a need to always include 4 tiles to get the full platform capability. Using just 2 E-core tiles might reach close to 256 cores, arriving at your desired configuration. The beautiful thing is that these are late binding decisions, that rely solely on backend packaging processes.

AMD isn't using Zen 4c for super core count either. According to what Charlie revealed at an analyst conference he said the 128 core Bergamo has twice the performance of Milan. Meaning Zen 3 level performance core wise. And you are going to have 128 core Genoa too(even Intel expects this). So core count is not an advantage. Bergamo is expected to have up to 400W TDP just like Genoa.

The E cores are nowhere near that efficient power wise. 4x the cores will need to perform quite low per core. And generally the trend is the same, so if AMD is going in one direction it's likely Intel is too. Look at what ARM cloud chip vendors like Ampere is doing. AT review concluded even the TDP advantage isn't big, but it's about lower cost. The die is quite small at 350mm2 for 80 cores and 435mm2 for 128 cores on TSMC N7!

Interesting how @uzzi38 thinks Turin may have less than even 192 cores. That's what Greymon has leaked. Looks like we can't trust any leakers anymore. The two companies have successfully thwarted all leakers for now.

 

[ashFTW]

AMD isn't using Zen 4c for super core count either. According to what Charlie revealed at an analyst conference he said the 128 core Bergamo has twice the performance of Milan. Meaning Zen 3 level performance core wise. And you are going to have 128 core Genoa too(even Intel expects this). So core count is not an advantage. Power consumption and cost must be it.

Performance, efficiency, and cost are all important. Increasing the number of cores have to be balanced by increased I/O and memory bandwidth and efficiency. At the top, the trend is still bigger platforms, higher cores, higher TDP, but lower cost/performance.

The E cores are nowhere near that efficient power wise. 4x the cores will need to perform quite low per core. And generally the trend is the same, so if AMD is going in one direction it's likely Intel is too. Look at what ARM cloud chip vendors like Ampere is doing. AT review concluded even the TDP advantage isn't big, but it's about lower cost. The die is quite small at 350mm2 for 80 cores and 435mm2 for 128 cores on TSMC N7!

That’s true currently of Gracemont built with Intel 7. Let’s see if Intel 3 and follow on E-core designs change that. I would rather have more cores per socket and fewer sockets (without bottlenecks) even if each socket is more expensive. But this needs more thought and reading AT and other reviews. I’ll get back to you. Thanks!

 

[lobz]

Good luck trying to find AMD server hardware. At least where I live (U.A.E.), asking for AMD is met with blank stares. Even the Azure data centers here have only one Epyc based HBv2 series available with no option other than 120 cores.

There's also no taco truck in the street I live in. How the fudge people keep eating tacos all over the place is totally beyond me.

 

[uzzi38]

I posted them in another thread because they were on topic but I should really also post them here.

Power scaling for 2+8, 4+8 and 6+8:

https://media.discordapp.net/attachments/697380330864115792/988008861308944404/unknown-114.png

https://media.discordapp.net/attachments/682675911488700419/988008049581101106/unknown.png

 

[lobz]

that's actually quite impressive from the measly Zen 3+ from the rearview mirror

 

[uzzi38]

I don't think it'll quadruple Granite Rapids core count. It might double it at best for lower cost and better power efficiency for cloud workloads.

@ashFTW Falcon Shores features "anstrom era process", so 20A is a good expectation.

Also the roadmap seems to point to coming in 2024 like with Granite Rapids?



There's the earlier GNR slide that suggested two compute tiles with 60 cores each. Don't know how literally we can take that though.

@uzzi38 What you are saying kinda makes sense. If it's on 5nm then it's the same node. If Zen 5 core is a big uarch gain. Maybe something like 160 cores?

Sorry, I'm not going to comment on actual core counts for a while. But I just want to set expectations a bit knowing full well the current rumours are total BS.

 

[lobz]

Sorry, I'm not going to comment on actual core counts for a while. But I just want to set expectations a bit knowing full well the current rumours are total BS.

It's quite possible that the 256 number is the planned max of Zen 5c, being falsely attributed to Turin.