Discussion Intel current and future Lakes & Rapids thread

[DrMrLordX]

Why change the R designation now? R has always meant "desktop/NUC BGA".

 

[NostaSeronx]

Cannonlake is Summer 2018. (shrink of Skylake-X(14nm+) core)
Icelake is Spring 2019. (shrink of Cascade-X(14nm++) core)
// Rather, than be a new core like Sandy/Ivy to Haswell/Broadwell or Haswell/Broadwell to Skylake. It is a shrink of the existing Skylake Xeon core to a more productive 10nm node. Very little tweaks, and mostly just a shrink. Cannon/Ice being shrinks is a divestiture of Core while a new architecture is in the prime brain tank.

Tiger Lake is dead. It is going to be a "blank" Rapids SoC on 10HPM++ instead. At least it will launch with the server EP Sapphire Rapids version with the 10GP++ process.
// Tigerlake has been shifted to be the new architecture. It most likely will not keep its lake name. So, Tigerlake is replaced with a new CPU core under Rapids, and a new GPU core under Sound.

Intel has dropped support of their internal nodes for full support of the custom foundry nodes. (New PDKs w00t!)
// This is more big on the Atom side, where they can turn around the Atom core to various semi-customs(Spreadtrum) much faster than before.

On a side note... Jet and Flash Imprint Lithography is set to surpass EUVL by 2021.
- >300 WPH for 300mm and >180 WPH for 450mm
- 3D Patterning is being investigated (comp: 1D/2D BEOL)
- Simplified FEOL/MOL/BEOL process steps.
// Less Defects than EUV
// Actual support 450mm wafers for logic
// Faster chip manufacturing, etc.
// There is also a rumor that 600~650 mm wafers will be supported by 2025(sample) and 2026(production).
--> Intel, Dai Nippon, Canon, and more - fingers crossed, etc.

J-FIL allows a return to architecture and process. - Intel Research

///edit: take everything as wildly unfound conjecture as always.

 

[Glo.]

Why change the R designation now? R has always meant "desktop/NUC BGA".

Maybe simply: Coffee Lake - R(efresh)?

 

[IntelUser2000]

Why change the R designation now? R has always meant "desktop/NUC BGA".

You are confusing code-name R with product name R.

Kabylake-R is a mobile quad core Kabylake on 15W, with -U naming.

The Core i7 6685R is Skylake GT4e graphics.

 

[DrMrLordX]

You are confusing code-name R with product name R.

Oh. Hard not to get confused with some of Intel's product codes/names. Ugh.

 

[Bouowmx]

Are those DTX motherboards (2 expansion slots)? H310M-DGS and HDV: https://videocardz.com/75277/asrock-h370-h310-and-b360-motherboards-leaked

 

[ksec]

Cannonlake is Summer 2018. (shrink of Skylake-X(14nm+) core)
Icelake is Spring 2019. (shrink of Cascade-X(14nm++) core)
// Rather, than be a new core like Sandy/Ivy to Haswell/Broadwell or Haswell/Broadwell to Skylake. It is a shrink of the existing Skylake Xeon core to a more productive 10nm node. Very little tweaks, and mostly just a shrink. Cannon/Ice being shrinks is a divestiture of Core while a new architecture is in the prime brain tank.

Tiger Lake is dead. It is going to be a "blank" Rapids SoC on 10HPM++ instead. At least it will launch with the server EP Sapphire Rapids version with the 10GP++ process.
// Tigerlake has been shifted to be the new architecture. It most likely will not keep its lake name. So, Tigerlake is replaced with a new CPU core under Rapids, and a new GPU core under Sound.

Intel has dropped support of their internal nodes for full support of the custom foundry nodes. (New PDKs w00t!)
// This is more big on the Atom side, where they can turn around the Atom core to various semi-customs(Spreadtrum) much faster than before.

On a side note... Jet and Flash Imprint Lithography is set to surpass EUVL by 2021.
- >300 WPH for 300mm and >180 WPH for 450mm
- 3D Patterning is being investigated (comp: 1D/2D BEOL)
- Simplified FEOL/MOL/BEOL process steps.
// Less Defects than EUV
// Actual support 450mm wafers for logic
// Faster chip manufacturing, etc.
// There is also a rumor that 600~650 mm wafers will be supported by 2025(sample) and 2026(production).
--> Intel, Dai Nippon, Canon, and more - fingers crossed, etc.

J-FIL allows a return to architecture and process. - Intel Research

///edit: take everything as wildly unfound conjecture as always.

I thought the industry has decided on J-FIL for NAND and Memory while EUV for anything complex?

 

[DrMrLordX]

I thought the industry has decided on J-FIL for NAND and Memory while EUV for anything complex?

Try not to take anything he says seriously. His track record is truly awful.

 

[IntelUser2000]

Try not to take anything he says seriously. His track record is truly awful.

More like fan fiction.

You know sites online where people can post fan fiction freely? You can make up a story about your favorite fiction, branch it out in a way you fancy.

There's also tech fan fiction.

 

[NostaSeronx]

I thought the industry has decided on J-FIL for NAND and Memory while EUV for anything complex?

The industry is planning for both.

HVM Logic requirements;
- >120 wph
- <0.01 defect density

Those are expected to be hit by Canon...

Initial target market-
Toshiba—a leading flash memory manufacturer—became the first customer to investigate J-FIL technology for IC fabrication; and SK Hynix—a leading DRAM manufacturer—joined Toshiba in developing J-FIL for manufacturing.

Next target market-
To extend J-FIL to production of logic devices, a further decrease in defect densities by at least two orders of magnitude is required, which is also being explored by Canon and its partners.

1.1 is 2017, it will be need to be 1.1/100 to get into logic. Overall, it is expected to get there by 2019. Canon has so far hit every roadmap challenge with J-FIL. So, 2019 will be the starting point for J-FIL in logic. With production of J-FIL logic being two years after Canon hits HVM logic requirements. Which will be in 2019 where they get defect density to 0.01 pcs. By the time logic production hits in 2021 the defect density should be at 0.001 pcs.

 

[Eug]

I'm sure many of you have seen this already but in case you haven't:

https://www.anandtech.com/show/12533/intel-spectre-meltdown

Intel is announcing that they have developed hardware fixes for both the Meltdown and Spectre v2 vulnerabilities, which in turn will be implemented into future processors. Both the next version of Intel’s Xeon server/HEDT platform – Cascade Lake – as well as new 8th gen Core processors set to ship in the second half of this year will include the mitigations.

For those not up to date with their Intel codenames, Cascade Lake is the 14nm refresh of Intel’s current Skylake-E/X family. Little official information is available about Cascade Lake, but importantly for datacenter vendors, this lays out a clear timetable for when they can expect to have access to Meltdown and Spectre-hardened silicon for use in new virtual machine servers. Given that virtual machine hosts were among those at the greatest risk here – and more impacted by the performance regressions of the software Meltdown mitigations – this is understandably most crucial market for Intel to address.

Meanwhile for updating Intel’s consumer chips, this is a bit more nebulous. While Intel hasn’t shared the complete text of their announcement with us ahead of press time, their specific wording is that the changes will be included in 8th gen Core processors “expected to ship in the second half of 2018.” Intel hasn’t said what processor family these are (e.g. Cannon Lake?), or for that matter whether these are even going to be traditional consumer chips or just the Core HEDT releases of Cascade Lake. So there is a lot of uncertainty here over just what this will entail. In the interim we have reached out to Intel about how consumers will be able to identify post-mitigation chips, and while we’re still waiting on a more complete response, Intel has told us that they want to be transparent about the matter.

 

[csbin]

I'm sure many of you have seen this already but in case you haven't:

https://www.anandtech.com/show/12533/intel-spectre-meltdown

Intel is announcing that they have developed hardware fixes for both the Meltdown and Spectre v2 vulnerabilities, which in turn will be implemented into future processors. Both the next version of Intel’s Xeon server/HEDT platform – Cascade Lake – as well as new 8th gen Core processors set to ship in the second half of this year will include the mitigations.

For those not up to date with their Intel codenames, Cascade Lake is the 14nm refresh of Intel’s current Skylake-E/X family. Little official information is available about Cascade Lake, but importantly for datacenter vendors, this lays out a clear timetable for when they can expect to have access to Meltdown and Spectre-hardened silicon for use in new virtual machine servers. Given that virtual machine hosts were among those at the greatest risk here – and more impacted by the performance regressions of the software Meltdown mitigations – this is understandably most crucial market for Intel to address.

Meanwhile for updating Intel’s consumer chips, this is a bit more nebulous. While Intel hasn’t shared the complete text of their announcement with us ahead of press time, their specific wording is that the changes will be included in 8th gen Core processors “expected to ship in the second half of 2018.” Intel hasn’t said what processor family these are (e.g. Cannon Lake?), or for that matter whether these are even going to be traditional consumer chips or just the Core HEDT releases of Cascade Lake. So there is a lot of uncertainty here over just what this will entail. In the interim we have reached out to Intel about how consumers will be able to identify post-mitigation chips, and while we’re still waiting on a more complete response, Intel has told us that they want to be transparent about the matter.

https://www.computerbase.de/2018-02/cpu-intel-cannon-lake-grafik/


Cannon Lake (2+2/2+0) Microcode fix

 

[dooon]

Feb leaked slides.

 

[Dayman1225]

Intel has seperated "Icelake" into "Icelake-Client" and "Icelake-server" for GCC and LLVM/Clang Compilers.

Intel Icelake Server Chips To Support WBNOINVD & PCONFIG

 

[mikk]

8 subslices for ICL would be nice. Gen9 has only 3 subslices (3x8=24 EUs @GT2). A fully working Cannonlake GT2 would come with 40 EUs (5x8), if there are still 8 EUs in one subslice ICL GT2 would come with 64 EUs, but this is just a guessing at this point without further infos.

There is an update:

sseu->max_slices = 1;
+ sseu->max_subslices = 8;
+ sseu->max_eus_per_subslice = 8;

https://patchwork.freedesktop.org/patch/211605/


Pretty much confirms 8 EUs per subslice and 64 EUs overall for a fully enabled GT2. So it could be that Gen 11 LP supports 48 EUs and Gen11 regular 64 EUs.

 

[mikk]

And there is this:

+CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
+CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
+CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
+CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
+CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
+CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
+CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
+CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)")

https://patchwork.freedesktop.org/patch/205790/


The few Gen11 LP entries are based on a GT 1.5 I believe. Because with this entry: http://www.ozone3d.net/gpudb/score.php?which=538885

We can see it's a 0x8a5a device which is based on an GT 1.5.

 

[Dayman1225]

And there is this:


https://patchwork.freedesktop.org/patch/205790/


The few Gen11 LP entries are based on a GT 1.5 I believe. Because with this entry: http://www.ozone3d.net/gpudb/score.php?which=538885

We can see it's a 0x8a5a device which is based on an GT 1.5.

There is an update:


https://patchwork.freedesktop.org/patch/211605/


Pretty much confirms 8 EUs per subslice and 64 EUs overall for a fully enabled GT2. So it could be that Gen 11 LP supports 48 EUs and Gen11 regular 64 EUs.

Nice findings! 64EUs in GT2(non LP)sounds nice!

 

[jpiniero]

It would be extremely big compared to the rest of the processor though, comparable to the dual core GT3. Seems like a waste, esp since it will still get killed by Raven Ridge.

 

[Bouowmx]

The maximum number of slices in ICL 11 is 1

sseu->max_slices = 1;

No more GT3 and 4, as they have 2 and 3 slices, respectively.

 

[IntelUser2000]

No more GT3 and 4, as they have 2 and 3 slices, respectively.

That means there's no top end advancement.

The patch doesn't mean we'll get to see a 64EU device. The same page says Gen 10 Cannonlake can have 6 subslices, which makes it maximum of 48. There were leaks based on the Intel drivers that showed lot more Gen 9 versions, but we didn't see them all either.

 

[mikk]

That means there's no top end advancement.

There might be no need for a GT3 with Icelake because the next refresh called Tigerlake is coming with Gen12. GT3 SKUs were coming at least 6 months later at least in the past, they can bring something bigger with Tigerlake instead.

The patch doesn't mean we'll get to see a 64EU device. The same page says Gen 10 Cannonlake can have 6 subslices, which makes it maximum of 48. There were leaks based on the Intel drivers that showed lot more Gen 9 versions, but we didn't see them all either.

I have to disagree, it confirms that we will see 64 EUs for GT2 parts. Cannonlake is a bad example because it isn't even available and most versions were canceled. I haven't seen Cannonlake with Gen9 graphics, from where did you get this? I think you are confusing the older Coffeelake entries with a Cannonlake platform string which were mislabeled because of the Cannonlake PCH.

 

[IntelUser2000]

There might be no need for a GT3 with Icelake because the next refresh called Tigerlake is coming with Gen12. GT3 SKUs were coming at least 6 months later at least in the past, they can bring something bigger with Tigerlake instead.

GT2 looks like it'll remain the base configuration. That means an on-die GT3 or bigger configs will still take extra time. GT3 and up configs take extra time because core layout changes and needing proprietary connections like OPIO. But I can see a way to speed it up, and that's having the bigger GPUs on-package Kabylake-G style using EMIB.

So Intel will have to further split their lines. One, a fully integrated solution with GT2 graphics on-die. On-die solutions are unquestionably lower power and cost at consumer die sizes.

Two, is by having the GPU die separate from the CPU with GPU having EMIB'd HBM. That reduces TTM substantially and it allows Intel to bring even bigger configs. Perhaps a 4 slice version with 384EUs, assuming Gen 12 makes 96EU the GT2 config.

I have to disagree, it confirms that we will see 64 EUs for GT2 parts. Cannonlake is a bad example because it isn't even available and most versions were canceled. I haven't seen Cannonlake with Gen9 graphics, from where did you get this?

No, no, sorry for making it not clear. I was addressing two different things as an example that not all possibilities end up in a product. One, is the EU count. The known Cannonlake versions were 40EU, 72EU, and 104EU. Not using the maximum 8 subslices/EU. Second, is early leaks for Gen 9 entries showing that it had more versions that were available to us. It wasn't from the opensource site, but a leak from their drivers. It had GT1.5 versions for ULX chips, no-eDRAM GT3 chips, high end GT3e chips.

The only known one is so far, the 48EU GT2 LP. The non-LP could just be a 48EU version with higher clocks. While I won't say 64EUs are impossible, its not a guarantee either. The maximum affords Intel with the flexibility, but may not as with Cannonlake. It's not a big deal, as long as they bring the performance, perf/watt, and perf/mm2 up substantially either way.

 

[IntelUser2000]

https://patchwork.freedesktop.org/patch/205790/

The few Gen11 LP entries are based on a GT 1.5 I believe. Because with this entry: http://www.ozone3d.net/gpudb/score.php?which=538885

We can see it's a 0x8a5a device which is based on an GT 1.5.

Somehow, I missed this post. Nice find! That's what I wanted to see.

I can't see where the GT 0.5 is going to be used. The successor to Goldmont Plus can easily use GT1 version of that. 8EUs are very small.

 

[jpiniero]

I can't see where the GT 0.5 is going to be used. The successor to Goldmont Plus can easily use GT1 version of that. 8EUs are very small.

It'd effectively be a 2D only version of the IGP. So maybe a server or workstation product. Maybe HEDT?

 

[IntelUser2000]

It'd effectively be a 2D only version of the IGP. So maybe a server or workstation product. Maybe HEDT?

They never did, and that's the thing. The Xeon D and the Avoton/Denverton chips use 2D graphics from a 3rd party vendor. An example is the AST2400. AST2400 isn't just a video chip though, that's one of the many functions. Also, the server dies are separate, and don't feature an iGPU as part of the die in the first place.