Discussion Intel current and future Lakes & Rapids thread

[Zucker2k]

Newegg marketplace!!! Comparing retail vs scalper is taxing to the argument.

F5, F5, F5.

 

[lobz]

Quit posting 10 year old videos to back up your conspiracy theories. I got more recent videos of AMD partnering with Maxon to deliver better performance to their customers. Care to see them?

There's no conspiracy in stating that back then Maxon was full-on Intel. Not that they should be blamed for that, given what AMD had at the time

 

[lobz]

Yes. In Europe prices include VAT.

Sure, but EUR is also stronger than USD, the 2 effects should normally equalize each other out, meaning normally the USD price ends up being the EUR price as well. Lots of 'should' and 'normally' in there

 

[Hulk]

If this pricing holds then I would say Intel thinks they are on top again and are pricing accordingly. Pricing seems a little "cheeky" to me but we shall see what the market will bear.

 

[Abwx]

If this pricing holds then I would say Intel thinks they are on top again and are pricing accordingly. Pricing seems a little "cheeky" to me but we shall see what the market will bear.

11900K is the same price as a 5900X FTR, so not exactly priced accordingly in respect of perfs.

 

[DrMrLordX]

Quit posting 10 year old videos to back up your conspiracy theories. I got more recent videos of AMD partnering with Maxon to deliver better performance to their customers. Care to see them?

There's no conspiracy in stating that back then Maxon was full-on Intel. Not that they should be blamed for that, given what AMD had at the time

Is this the part where I have to remind everyone that Cinebench R20 and R23 both use Embree?

 

[Ajay]

While I doubt Apple will pursue SMT, just because the M1 doesn't have it enabled doesn't necessarily mean it isn't in there. That's not easy to get right given all the security issues that have been found with it over the past few years, so even if they wanted to do it they might need an iteration or two before they would announce/enable it.

I don’t see the point of Apple ever spending xtors and floor plan on SMT when they already are spending both on small cores. Intel's line of cores has been SMT for a long time; and those cores are also in Xeons. Hence the different approach, at least for now.

 

[Mopetar]

Eventually SMT will be the easiest way to add performance. Perhaps Apple has been experimenting with it. AMD showed they were able to do better than Intel. Perhaps Apple wants to do better still.

 

[eek2121]

Today Intel claims that Cinebench is useless, or it is not useful real world bench.

If we now, that Cinebench dont care about system memory performanse+dont care about big L3 Cache.Hm, what has changed from R20 to R23.

Quit posting 10 year old videos to back up your conspiracy theories. I got more recent videos of AMD partnering with Maxon to deliver better performance to their customers. Care to see them?

Anyone who feels the need to use bold, colored fonts or outdated videos, articles, or far fetched rumors to make a point should honestly be ignored by everyone else. Cinebench is actually expected to be one of the benchmarks showcased at the ADL-S launch event. SPEC and Cinebench will likely be used by Intel. A handful of games will also be shown, but from what I know, the list hasn't been decided. What I do know is that all of this doomsay about gaming performance is definitely unwarranted at this point in time. ADL-S will end up being an excellent gaming chip. I can promise you that!

For me personally, I'm not actively looking to upgrade, but when Zen3D is released I'm going to look at both platforms. I doubt either will provide a decent upgrade over my 5950x, but one can hope...

 

[diediealldie]

Look at the Monts IPC. I'm quite curious what will next Monts be. Since Raptor Cove will be using refined Gracemont, probably we're gonna see a new small core in Meteor Lake...

Using the Cinebench 20 data below I isolated Golden Cove and Gracemont MT and "Single Core" scores. Used simultaneous equations with 12700K and 12900K data. Then used other data to calculate the numbers below. Take with a grain of salt of course.

UPDATE - I calculated IPC increase incorrectly. New chart is correct.

 

[Abwx]

Is this the part where I have to remind everyone that Cinebench R20 and R23 both use Embree?

It is used starting with CB R15.

Cinema 4D - Wikipedia

en.wikipedia.org

 

[DrMrLordX]

It is used starting with CB R15.

Not necessarily. For a long time, Maxon allowed divergence of the Cinebench and Cinema4D code bases. R20 was the first Cinebench to actually use Embree so far as I can tell (unlike Cinema4D which as supported it since R15).

If you read the press releases for Cinebench R20, you'll note everyone making a big deal about the inclusion of Embree support.

 

[Abwx]

Not necessarily. For a long time, Maxon allowed divergence of the Cinebench and Cinema4D code bases. R20 was the first Cinebench to actually use Embree so far as I can tell (unlike Cinema4D which as supported it since R15).

If you read the press releases for Cinebench R20, you'll note everyone making a big deal about the inclusion of Embree support.

Quite possible, if we look at the relative scores between Intel and AMD CPUs in respect of the version we can see that each revision since R15 has brought an advantage to Intel in respect of the previous test.

That being said CB is still a very usefull bench that more or less manage to give an accurate idea of a CPU throughput, at the time of the FX8150 a Cinema 4D rep posted at RWT to state that their bench was relevant and optimised for all CPUs...

 

[Ajay]

Eventually SMT will be the easiest way to add performance. Perhaps Apple has been experimenting with it. AMD showed they were able to do better than Intel. Perhaps Apple wants to do better still.

Why, Apple’s designs are very wide with a high level of ILP? SMT is a way to sustain high ILP. Why spend more xtors on something they already have achieved. They will have a lower SMT rate than Intel and AMD - one cannot get blood from a stone.

 

[BorisTheBlade82]

@Ajay
TBH as I see it, it is the other way around. A very wide architecture just like a very deep architecture is difficult to feed. I know that Apple did a lot to maintain a high ILP. But for me it is simply hard to believe that there is no significant SMT potential in M1, because there is only so much you can do if instructions fail to be in your desired mixture and your pipeline is already stalling. Ofc I am only an armchair expert, so history might tell.

 

[coercitiv]

Intel CEO Pat Gelsinger: The Silicon Man With The Software Plan

One of the things that I’ve learned in my 11-year ‘vacation’ [at VMware and EMC] is delivering silicon that isn’t supported by software is a bug. We have to deliver the software capabilities, and then we have to empower it, accelerate it, make it more secure with hardware underneath it. And to me, this is the big bit flip that I need to drive at Intel.

To me it looks more and more like Gelsinger is the real deal, he has made Intel aware that it needs to execute consistently on all fronts: arch, node, software. Now, if I'm allowed a cherry on top this holiday season, may we have leading edge marketing as well? No?! Fine, fair enough, at least stop screwing with the mobile SKU names and make them readable by humans!

PS, bonus quote from the article:

We have these efficiency cores and performance cores. Don’t just leave it up to the operating system to decide what to do. Let the OEMs, ODMs and the channel partners have access to APIs that can do whatever they want to do, let’s say, in telco or at the edge

Greg Lavender , Intel CTO

 

[Mopetar]

Why, Apple’s designs are very wide with a high level of ILP? SMT is a way to sustain high ILP. Why spend more xtors on something they already have achieved. They will have a lower SMT rate than Intel and AMD - one cannot get blood from a stone.

Doesn't matter how wide your architecture is if there's a branch mis-prediction that needs to fetch something that isn't in the cache before it can do anything else. If there's enough spare cycles then SMT can make use of all of those resources that are just sitting there and waiting.

Adding bigger caches can alleviate that and I think Apple has generally favored shorter pipelines so that the penalties aren't as bad, but eventually SMT becomes the best solution for a given transistor budget.

It's certainly more beneficial in a desktop environment where there are a lot of applications running and plenty of threads. iOS has an easier time since there's far less background processing and apps that aren't actively being used are suspended for the most part.

 

[BorisTheBlade82]

@Mopetar
The argument in your last paragraph makes a lot of sense to me when taking the re-use of functional blocks into account.

 

[Doug S]

Eventually SMT will be the easiest way to add performance. Perhaps Apple has been experimenting with it. AMD showed they were able to do better than Intel. Perhaps Apple wants to do better still.

SMT only helps throughput if you have more work than your existing cores can handle. How often is someone pegging all six cores in an iPhone?

For Macs it may be worth it, and maybe we'll see it on the Mac Pro, but for phones it is IMHO a ridiculous idea.

 

[DrMrLordX]

To me it looks more and more like Gelsinger is the real deal, he has made Intel aware that it needs to execute consistently on all fronts: arch, node, software.

To me he's just saying, "No more Itanium, okay?". And yes I know that Itanium is dead, but Gelsinger doesn't want to oversee the introduction of another uarch family with capabilities that will go broadly-unsupported by developers. Either Intel will have to stick to the existing software paradigm or they'll have to provide the tools to developers all up and down the chain to utilize new hardware capabilities.

 

[Ajay]

@Ajay
TBH as I see it, it is the other way around. A very wide architecture just like a very deep architecture is difficult to feed. I know that Apple did a lot to maintain a high ILP. But for me it is simply hard to believe that there is no significant SMT potential in M1, because there is only so much you can do if instructions fail to be in your desired mixture and your pipeline is already stalling. Ofc I am only an armchair expert, so history might tell.

The penalty for a stall in a high speed, narrow, deep pipeline is, IIRC, worse for than for a wide, shorter pipeline (all else being equal, which isn't exactly the case). It comes down to where Apple should use more stores to get the best performance. Perhaps, going forward, if Apple lengthens the pipelines of it large cores for higher-end MXX chips, it would make more sense to add some level of SMT as Intel & AMD do. This is my two cents. Apple, of course, knows how they want spend xtors and die space much better than I .

 

[Ajay]

To me he's just saying, "No more Itanium, okay?". And yes I know that Itanium is dead, but Gelsinger doesn't want to oversee the introduction of another uarch family with capabilities that will go broadly-unsupported by developers. Either Intel will have to stick to the existing software paradigm or they'll have to provide the tools to developers all up and down the chain to utilize new hardware capabilities.

I think, among other things, he is talking about embedding Intel engineers with large software makers. This is what Nvidia has done with AAA gaming companies and big AI software vendors. Well, lately, probably allot of video conferences. Nvidia will actually write code in some instances for it's top level partners (ergo - "the way it's meant to be played').

 

[DrMrLordX]

I think, among other things, he is talking about embedding Intel engineers with large software makers.

Yeah, probably. Intel will probably provide direct support to some high-profile FOSS projects as well. In fact they've been doing that for years in some capacity.

 

[moinmoin]

We have to deliver the software capabilities, and then we have to (...) make it more secure with hardware underneath it.

I sure hope he keeps his words and this will lead to a paradigm shift at Intel ensuring security first at the chip design level. Currently it's rather like the software has to make the hardware secure than the other way around.

Intel will probably provide direct support to some high-profile FOSS projects as well. In fact they've been doing that for years in some capacity.

Intel's FOSS support is pretty outstanding already.

 

[eek2121]

I think, among other things, he is talking about embedding Intel engineers with large software makers. This is what Nvidia has done with AAA gaming companies and big AI software vendors. Well, lately, probably allot of video conferences. Nvidia will actually write code in some instances for it's top level partners (ergo - "the way it's meant to be played').

This is the correct answer, and it is an area where I will argue AMD is lacking. For example, a lot of people complain about thread usage and gaming. Imagine a set of libraries that takes advantage of both P/E cores. A game might only use 20-30w on an Intel system vs. 100-115w on the AMD system. As someone with game engine development experience, back in the day, I would have killed for a small, power efficient core to dump some of my code off from.

We will have to see how well Intel executes here, but as a software and hardware engineer, I have been intrigued for a while. I just hope they can improve power consumption over the last 3 generations…

Anyway. I probably won’t be around much for the next 2 months due to a medical issue, but I hope to read the forum from time to time along with the reviews.