I've updated this enough at this point that I'm reposting it along with links to all of the sources.
Alder Lake (ADL)
manufacturing process:
Intel 10nm Enhanced SuperFin (10+++ > 10++ > 10ESF)
dies:
2+8+2 LP = 2 Golden Cove cores + 8 Gracemont cores + GT2 graphics + 4 Thunderbolt 4 ports (Intel Family 6, Model 154, Stepping 1?)
6+8+2 LP = 6 Golden Cove cores + 8 Gracemont cores + GT2 graphics + 4 Thunderbolt 4 ports (Intel Family 6, Model 154, Stepping 0?)
6+0+1 HP = 6 Golden Cove cores + GT1 graphics (Intel Family 6, Model 151, Stepping ?)
8+8+1 HP = 8 Golden Cove cores + 8 Gracemont cores + GT1 graphics (Intel Family 6, Model 151, Stepping 1?)
*Golden Cove cores support Hyper-Threading and AVX-512
graphics:
GT1 = 32EU Xe-LP Gen12.2
GT2 = 96EU Xe-LP Gen12.2
chipsets:
ADP-LP = 600 Series on-package PCH, OPI x8 @ 4 GT/s
ADP-H = 600 Series PCH (2-chip platform), DMI Gen4 x8, 28 mm x 25 mm
*Alder Lake PCH = Alder Point (ADP), Intel 14nm
packages:
M = BGA 1781, ? (Y > Type 4 > UP4 > M)
P = BGA 1744, 50 mm x 25 mm (U > Type 3 > UP3 / H35 > P)
S BGA = BGA ?, ? (H > S BGA)
S = LGA 1700, 45 mm x 37.5 mm
memory interfaces:
M = LPDDR4X-4266 / LPDDR5-5400?
P = LPDDR4X-4266 / LPDDR5-5400? / DDR4-3200 1DPC / DDR5-4800 1DPC
S = DDR4-3200 2DPC / DDR5-4000 2DPC / DDR5-4800 1DPC
PCI Express:
M = CPU Gen5 1x8 / Gen4 1x4?, PCH Gen3 up to 10 lanes
P = CPU Gen5 1x8 + Gen4 2x4, PCH Gen3 up to 12 lanes
S = CPU Gen5 1x16 / 2x8 + Gen4 1x4, PCH Gen4 up to 16 lanes + Gen3 up to 12 lanes
platforms:
M5 = 2+8+2 LP and TGP-LP? dies, M package
U9 = 2+8+2 LP and TGP-LP? dies, M package
U15 = 2+8+2 LP and ADP-LP dies, P package
U28 = 6+8+2 LP and ADP-LP dies, P package
H45 = 6+8+2 LP and ADP-LP dies, P package
H55 = 8+8+1 HP die, S BGA package
S35 = 6+0+1 HP or 8+8+1 HP die, S package
S65 = 6+0+1 HP or 8+8+1 HP die, S package
S80 = 6+0+1 HP or 8+8+1 HP die, S package
S125 = 8+8+1 HP die, S package
launch schedule:
ADL-M/P 2+8+2 (M5/U9/U15) Aug '21? press embargo
ADL-P 6+8+2 (U28) Aug '21? press embargo
ADL-S 8+8+1 WW35'21 start of volume production > NET Dec '21 RTS
ADL-S 6+0+1 WW41'21 start of volume production > NET Jan '22 RTS
ADL-P 6+8+2 (H45) Jan '22? press embargo
ADL-S 8+8+1 (H55) Apr '22? press embargo
sources:
sharkbay PTT BBS 2020-01-02
sharkbay PTT BBS 2020-03-02
sharkbay PTT BBS 2020-05-13
@JZWSVIC Zhihu 2020-07-12
sharkbay PTT BBS 2020-07-15
Li Tang Technology interposer list
Coelacanth's Dream Alder Lake
Intel Architecture Day 2020-08-13
Notebookcheck 2020-10-03
Intel CES 2021-01-11
HXL @9550pro Twitter 2021-03-06
VideoCardz 2021-03-11
VideoCardz 2021-03-20
188号 @momomo_us Twitter 2021-03-26
HXL @9550pro Twitter 2021-04-16
edit: added links to additional sources
Alder Lake (ADL)
manufacturing process:
Intel 10nm Enhanced SuperFin (10+++ > 10++ > 10ESF)
dies:
2+8+2 LP = 2 Golden Cove cores + 8 Gracemont cores + GT2 graphics + 4 Thunderbolt 4 ports (Intel Family 6, Model 154, Stepping 1?)
6+8+2 LP = 6 Golden Cove cores + 8 Gracemont cores + GT2 graphics + 4 Thunderbolt 4 ports (Intel Family 6, Model 154, Stepping 0?)
6+0+1 HP = 6 Golden Cove cores + GT1 graphics (Intel Family 6, Model 151, Stepping ?)
8+8+1 HP = 8 Golden Cove cores + 8 Gracemont cores + GT1 graphics (Intel Family 6, Model 151, Stepping 1?)
*Golden Cove cores support Hyper-Threading and AVX-512
graphics:
GT1 = 32EU Xe-LP Gen12.2
GT2 = 96EU Xe-LP Gen12.2
chipsets:
ADP-LP = 600 Series on-package PCH, OPI x8 @ 4 GT/s
ADP-H = 600 Series PCH (2-chip platform), DMI Gen4 x8, 28 mm x 25 mm
*Alder Lake PCH = Alder Point (ADP), Intel 14nm
packages:
M = BGA 1781, ? (Y > Type 4 > UP4 > M)
P = BGA 1744, 50 mm x 25 mm (U > Type 3 > UP3 / H35 > P)
S BGA = BGA ?, ? (H > S BGA)
S = LGA 1700, 45 mm x 37.5 mm
memory interfaces:
M = LPDDR4X-4266 / LPDDR5-5400?
P = LPDDR4X-4266 / LPDDR5-5400? / DDR4-3200 1DPC / DDR5-4800 1DPC
S = DDR4-3200 2DPC / DDR5-4000 2DPC / DDR5-4800 1DPC
PCI Express:
M = CPU Gen5 1x8 / Gen4 1x4?, PCH Gen3 up to 10 lanes
P = CPU Gen5 1x8 + Gen4 2x4, PCH Gen3 up to 12 lanes
S = CPU Gen5 1x16 / 2x8 + Gen4 1x4, PCH Gen4 up to 16 lanes + Gen3 up to 12 lanes
platforms:
M5 = 2+8+2 LP and TGP-LP? dies, M package
U9 = 2+8+2 LP and TGP-LP? dies, M package
U15 = 2+8+2 LP and ADP-LP dies, P package
U28 = 6+8+2 LP and ADP-LP dies, P package
H45 = 6+8+2 LP and ADP-LP dies, P package
H55 = 8+8+1 HP die, S BGA package
S35 = 6+0+1 HP or 8+8+1 HP die, S package
S65 = 6+0+1 HP or 8+8+1 HP die, S package
S80 = 6+0+1 HP or 8+8+1 HP die, S package
S125 = 8+8+1 HP die, S package
launch schedule:
ADL-M/P 2+8+2 (M5/U9/U15) Aug '21? press embargo
ADL-P 6+8+2 (U28) Aug '21? press embargo
ADL-S 8+8+1 WW35'21 start of volume production > NET Dec '21 RTS
ADL-S 6+0+1 WW41'21 start of volume production > NET Jan '22 RTS
ADL-P 6+8+2 (H45) Jan '22? press embargo
ADL-S 8+8+1 (H55) Apr '22? press embargo
sources:
sharkbay PTT BBS 2020-01-02
sharkbay PTT BBS 2020-03-02
sharkbay PTT BBS 2020-05-13
@JZWSVIC Zhihu 2020-07-12
sharkbay PTT BBS 2020-07-15
Li Tang Technology interposer list
Coelacanth's Dream Alder Lake
Intel Architecture Day 2020-08-13
Notebookcheck 2020-10-03
Intel CES 2021-01-11
HXL @9550pro Twitter 2021-03-06
VideoCardz 2021-03-11
VideoCardz 2021-03-20
188号 @momomo_us Twitter 2021-03-26
HXL @9550pro Twitter 2021-04-16
edit: added links to additional sources
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