- Oct 14, 2003
It's likely just an easy way of integrating Gracemont cluster to Alderlake and it's ring. Having a dual/quad core cluster sharing L2 has been true all the way since Silvermont in 2013.Hmm, haven't followed the 'mont cores at all really, but why have both a shared L2$ and shared L3$ per four core cluster?
L2$ is probably inclusive and L3$ victim; sharing L2$ seems pretty old skool.
The low cost/low power versions that will be branded Celerons and Pentiums will likely have the same configuration, just without the L3 cache. The Grand Ridge base station SoC also does not have L3 cache.
Or, doubling L1I is a perfect low hanging fruit improvement in a dual decode cluster architecture. The L1 Instruction cache feeds the two decoders. In a scenario where maximum decode width is utilized, in Tremont it's similar to halving L1I size per decoder.What is also interesting is 64KB L1I cache for Gracemont, Intel probably realized that without uCode cache L1I is glass jaw of performance and are increasing it from 32KB in Tremont to 64KB in Silvermont.
Further reinforcing the fact that it's not based on an architecture that should have retired(Skylake), but an entirely new one.While Tremont microarchitecture did not build a dynamic mechanism to load balance the decode clusters, future generations of Intel Atom processors will include hardware to recognize and mitigate these cases without the need for explicit insertions of taken branches into the assembly code.