Discussion Intel current and future Lakes & Rapids thread

[mikk]

The expectation that Alder Lake will have any significant GPU improvements over Tiger Lake.

What is a significant GPU improvement for you?

 

[Hitman928]

My understanding is those are per core numbers, not per SOC... otherwise I'd love to find out more about what kind of real-world workload uses just 1W on TGL-U.

The 'leak' sure makes it sound like it is supposed to be SOC power:

One final note is that these measurements are from the SoC alone, not an entire system

One important note: this Alder Lake P processor is equipped with two Cove cores, eight Atom cores, and the faster iGPU variant. By relying on so many Atom cores, Intel is able to greatly improve power consumption in everything but idle

 

[Exist50]

What is a significant GPU improvement for you?

Put it this way. I think anything over 20% gain would be very optimistic.

 

[repoman27]

edit: I posted an updated version.

I was getting confused with the mapping of dies to packages to platforms for Alder Lake so I compiled a little cheat sheet. I kept adding to it, so now it contains a bunch of info from various sources. I figured I'd post it here in case anyone else finds it useful.

Alder Lake (ADL)

manufacturing process:
Intel 10nm Enhanced SuperFin (10+++ > 10++ > 10ESF)

dies:
2+8+2 LP = 2 Golden Cove cores + 8 Gracemont cores + GT2 graphics + 4 Thunderbolt 4 ports
6+8+2 LP = 6 Golden Cove cores + 8 Gracemont cores + GT2 graphics + 4 Thunderbolt 4 ports
6+0+1 HP = 6 Golden Cove cores + GT1 graphics
8+8+1 HP = 8 Golden Cove cores + 8 Gracemont cores + GT1 graphics

graphics:
GT1 = 32EU Xe-LP Gen12.2
GT2 = 96EU Xe-LP Gen12.2

chipsets:
Alder Lake PCH = Alder Point (ADP), Intel 14nm
ADP-LP = 600 Series on-package PCH, OPI x8 @ 2 or 4 GT/s
ADP-H = 600 Series PCH (2-chip platform), DMI Gen4 x8

packages:
M = BGA 1781 (Y > Type 4 > UP4 > M)
P = BGA 1744 (U > Type 3 > UP3 / H35 > P)
S BGA = BGA ? (H > S BGA)
S = LGA 1700

memory interfaces:
M = LPDDR4X-4266 / LPDDR5-?
P = LPDDR4X-4266 / LPDDR5-? / DDR4-3200 1DPC / DDR5-4800 1DPC
S = DDR4-3200 2DPC / DDR5-4000 2DPC / DDR5-4800 1DPC

PCI Express:
M = ?
P = CPU Gen5 1x8 + Gen4 2x4, PCH Gen3 up to 12 lanes
S = CPU Gen5 1x16 + Gen4 1x4, PCH Gen4 up to 16 lanes + Gen3 up to 12 lanes

platforms:
M5 = 2+8+2 LP die, M package
U9 = 2+8+2 LP die, M package
U15 = 2+8+2 LP die, P package
U28 = 6+8+2 LP die, P package
H45 = 6+8+2 LP die, P package
H55 = 8+8+1 HP die, S BGA package
S35 = 6+0+1 HP or 8+8+1 HP die, S package
S65 = 6+0+1 HP or 8+8+1 HP die, S package
S80 = 6+0+1 HP or 8+8+1 HP die, S package
S125 = 8+8+1 HP die, S package

launch schedule:
ADL-M/P 2+8+2 (M5/U9/U15) Aug '21? press embargo
ADL-P 6+8+2 (U28) Aug '21? press embargo
ADL-S 8+8+1 WW35'21 start of volume production > NET Dec '21 RTS
ADL-S 6+0+1 WW41'21 start of volume production > NET Jan '22 RTS
ADL-P 6+8+2 (H45) Jan '22? press embargo
ADL-S 8+8+1 (H55) Apr '22? press embargo

There's still a few question marks on there, but we already seem to know an awful lot of details about Intel's upcoming releases for the next 12 months.

 

[coercitiv]

dies:
6+0+1 HP = 6 Golden Cove cores + GT1 graphics

There's a separate ADL die with big cores only?

 

[repoman27]

There's a separate ADL die with big cores only?

Yes:

https://twitter.com/i/web/status/1382966601654276100

and

sharkbay : 家族表: ADL -S(881/601) -P(282/682) -M(282)

source: https://www.ptt.cc/bbs/PC_Shopping/M.1594785680.A.0EC.html

 

[TESKATLIPOKA]

There's a separate ADL die with big cores only?

I don't think It's a separate die, more like the small cores are just disabled. Here is the link videocardz

 

[jpiniero]

The 6+0+1 is for desktop i3 and below although I suppose that also include the low end i5.

 

[repoman27]

I don't think It's a separate die, more like the small cores are just disabled. Here is the link videocardz

Binning and blowing fuses generally wouldn't get its own production window on an Intel dashboard—pretty sure it's a separate die.

Although ICL-64L is almost certainly using the same dies as ICL-SP, all of which ship with 64 PCIe lanes enabled anyway, so I'm not sure why Intel is using that suffix or focusing on 64 lanes at all in that slide. As Ian noted, it looks like the XCC die actually has 80 PCIe lanes present. Maybe they had hoped to (or perhaps eventually will) enable all 80 lanes on certain SP parts?

edit: Just as a general observation, ADL represents a full client product stack from 5 W to 125 W with just 4 dies, all on 10ESF. If this turns out as planned, it would finally mark the end of Intel's split process strategy and be their first top to bottom 10nm line-up.

 

[TESKATLIPOKA]

Binning and blowing fuses generally wouldn't get its own production window on an Intel dashboard—pretty sure it's a separate die.

1. Why would they make a separate die with only Golden Cove cores and no Gracemont cores?
2. What market would It be aimed at?
3. If It was for desktop gaming then I would also expect an 8 core, no info about that so far
4. Standard Alder Lake is already planned for Desktop, so this one looks unnecessary in my opinion.

 

[jpiniero]

1. Why would they make a separate die with only Golden Cove cores and no Gracemont cores?

Because it's smaller. It's just the 8+8 die with 2 big cores and the small cores cut out. Smaller die, more chips per wafer, etc, etc.

2. What market would It be aimed at?

Low end desktop.

 

[Exist50]

1. Why would they make a separate die with only Golden Cove cores and no Gracemont cores?
2. What market would It be aimed at?
3. If It was for desktop gaming then I would also expect an 8 core, no info about that so far
4. Standard Alder Lake is already planned for Desktop, so this one looks unnecessary in my opinion.

Cost. 8+8 would be overkill for the vast majority of OEM PCs. Having a 6+0 die gives a much more cost effective option to address that market, as well as a cost-effective way to bin down to 4 cores.

 

[jpiniero]

Cost. 8+8 would be overkill for the vast majority of OEM PCs. Having a 6+0 die gives a much more cost effective option to address that market, as well as a cost-effective way to bin down to 4 cores.

There will be 2 core models too. I dunno if Intel is going to really do 6+0 for i3, 4+0 for Pentium and 2+0 for Celeron but I suppose that could be the end result.

 

[Exist50]

There will be 2 core models too. I dunno if Intel is going to really do 6+0 for i3, 4+0 for Pentium and 2+0 for Celeron but I suppose that could be the end result.

I feel like 2c would be too low end by that point. Risk too much intersection with the N series. But Intel's segmentation choices have been baffling before.

 

[jpiniero]

I feel like 2c would be too low end by that point. Risk too much intersection with the N series. But Intel's segmentation choices have been baffling before.

Celeron and Pentium Gold are just a dumping ground for bad dies. It's kind of designed to be limiting.

Give the Celeron HT and the IPC gain of Golden Cove over Skylake, that's a big improvement there.

 

[mikk]

Are you still sticking to that? How long ago was that from? Give it up already. So you don't have a problem with them saying Tigerlake is the best CPU ever made and that Xe would be a game changer? Or that they were hyping it for 6 months? Xe is decent but nothing to be super excited about. 10-30% advantage in graphics over competition using 2 generations old is their best effort? And they have glitches in games that are over a decade old?

It's a heads up for you. Your claims are sometimes....let's say bold. You have proven wrong more than once, you should be a bit more cautious and why should I give up? You did wrong not me! Also you should now better that on DDR4/LPDDR4 you can't expect big differences, the next big iGPU performance upgrade will most likely require DDR5 or LPDDR5. Intel is coming from really low, Icelake and Tigerlake both doubled the performance. You cannot expect a doubling every generation and it's telling you can't give them some credits for their progress. Once they started matching or beating AMD iGPUs the excuses roll in and Rembrandt is your next big hope.

 

[Shivansps]

I still wondering about what they are going to do with Celerons and Pentiums. They still need to make the Gracemont Atoms for mobile, how crazy would be to come up with a 8C Gracemont and 64 EU for a Pentium?.

 

[jpiniero]

I still wondering about what they are going to do with Celerons and Pentiums. They still need to make the Gracemont Atoms for mobile, how crazy would be to come up with a 8C Gracemont and 64 EU for a Pentium?.

Appears that the mobile Pentium/Celeron will be 1+4 with 48 EUs. I imagine that is still subject to change.

 

[IntelUser2000]

After looking at Pentium N6005 which is a 4C Tremont 2GHz base with a 10W TDP, then I can say I was at least with Gracemont's base frequencies.

Actually, N5000 running at 6W can clock 2GHz in multi-threaded workloads like Cinebench. The N5030 Refresh based on it's performance clocks at 2.2-2.3GHz. Since the Tremont N6000 performs 30% above that, at the same 6W it can clock at least 2.3GHz.

Even Lakefield with 5W TDP runs it's Tremont cores at 1.8GHz.

The N6005 at 10W performs an additional 20% faster, meaning in MT workloads it can sustain 2.8-3GHz clocks.

I think I'll need to see some evidence of Intel's big core SOCs idling at 0.1W or doing any kind of real activity whatsoever at 1W or less (bursty or not) before I give Adored's charts any credence. I have yet to see anything like that from any of Intel's big core SKUs.

There's a decently sized thread in Notebookreview forums where this one guy goes through all the tips on increasing battery life.

Here's the link to the OP getting 1.0W on his Y CPU under these conditions:

Here is my CPU with 4 chrome tabs, youtube playing in the background, and a few word documents open.

TechnologyGuide

Thank you for visiting the TechnologyGuide network. Unfortunately, these forums are no longer active. We extend a heartfelt thank you to the entire community for their steadfast support—it is really you, our readers, that drove

forum.notebookreview.com

That's a Kabylake-Y. He says his friend's Broadwell-Y setup can idle at 0.2W package power, and it's under Throttlestop which will have some activity, nevermind being unable to completely control a real-time OS like Windows.

M5 = 2+8+2 LP die, M package

Alderlake-M is 1+4 with 64EUs, not 2+8 with 96EUs.

 

[IntelUser2000]

Once they started matching or beating AMD iGPUs the excuses roll in and Rembrandt is your next big hope.

Don't you have better things to do than attack someone in forums? Trust me, I like Intel too, but watching them fumble over and over again(and for most of the two decades I might add) is sad and depressing to watch. I do not think liking someone/something means justifying their screwups.

I give credit where it's due. And AMD is doing fantastic. RDNA and RDNA2 came out to be exactly as AMD stated - 50% improved performance per watt over the predecessor. While I do not believe full benefits will be shown on mobile since it's already operating at an efficient power envelope, I believe they'll take the graphics lead again, and by a noticeable amount.

And don't rely on DDR5 being the sole savior for Xe. They nearly quadrupled the performance between Gen 9 and Gen 12 with basically the same bandwidth. And AMD has further optimizations to go - such as sharing the L3 memory, and better memory compression and occlusion techniques.

Nevermind how Intel is noticeably behind in driver quality. It's Intel that needs to prove in graphics - not AMD.

 

[jpiniero]

Alderlake-M is 1+4 with 64EUs, not 2+8 with 96EUs.

No I think 2+8+96 is right although the 5W version only gets 1+4+64.

 

[TESKATLIPOKA]

Because it's smaller. It's just the 8+8 die with 2 big cores and the small cores cut out. Smaller die, more chips per wafer, etc, etc.

Low end desktop.

Cost. 8+8 would be overkill for the vast majority of OEM PCs. Having a 6+0 die gives a much more cost effective option to address that market, as well as a cost-effective way to bin down to 4 cores.

Guys, I don't have a problem with Intel releasing a separate die with fewer cores, because as you mentioned It's more cost-effective etc, etc.
I just don't understand why they want to make a separate die with only big cores and no small cores. Why don't they use some mobile version or make a 4+8 32EU variant instead If the IGP is too big? I am expecting that 4 small cores are not much bigger than a single big core, the same as with Lakefield.
The only possibility I see is that 6 cores would perform better within 6 threaded apps than a 4+8 version, where I expect the small core having ~1/2 of the big core's performance.

 

[TESKATLIPOKA]

No I think 2+8+96 is right although the 5W version only gets 1+4+64.

As you said Alder Lake M also has a 2+8+96EU version with 9W TDP.

 

[Magic Carpet]

It’s interesting to see how fast Windows Scheduler adapts to these newer cpus. I know, that it took a Windows release for AMD Thuban to properly boost its cores (Didn’t work as intended in Windows 7 OOTB). Shouldn’t take long, I’d imagine since we on a faster cycle now, but still interesting.

 

[jpiniero]

Guys, I don't have a problem with Intel releasing a product with less cores, because as you mentioned It's more cost effective etc, etc.
I just don't understand why they plan a separate die with only big cores and no small cores. Why don't they use some mobile version or make a 4+8 32EU variant instead If the IGP is too big? I am expecting that 4 small cores are not much bigger than a big core, the same as with Lakefield.

Could be a combination of marketing and yields. Say the lowest i5 is 6+4 or 6+0... can't have the i3 being 4+8 for marketing reasons. Also gives them a place to dump all of the bigger die chips that have both small core clusters busted.