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Discussion Intel current and future Lakes & Rapids thread

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Lodix

Senior member
Jun 24, 2016
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It takes more time than just a quarter or two to go from risk production to actual volumen production and then get the product to the market.
 

Ajay

Diamond Member
Jan 8, 2001
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I'm sure the majority of you all have already seen this from the Coffee Lake thread - but I thought it was appropriate to post it here
Intel is now targeting performance improvements, power reductions & area shrinks in successive 10nm nodes. New ball game for Intel. Intel is now behaving more like the pure fabs with incremental improvements. Interesting times - Intel needs EMIB yesterday!
 

Ajay

Diamond Member
Jan 8, 2001
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It's horrible because TSMC is going HVM with their 7nm SoC node like half a year earlier.

That's not how you get design wins.
Intel will have better performance and TSMC better density - if history is any guide. ARM just doesn't need Intel's better parametric performance right now. It also seems really difficult for Intel to offer good pricing to designers even at lower densities. The integrated designer/fab model is Intel's strength in x86 and weakness in everything else.
 
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Ajay

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Jan 8, 2001
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It's neither actually. N7 is better AND earlier.
We don't know anything about Intel's 7nm yet. My comment was based on history - there is no factual basis for making what you claim now - except, obviously, the 'earlier' part.
If you are simply here to bash Intel and root for 'anybody but Intel' then please find another thread. This one isn't the one you want.
 
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jpiniero

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Oct 1, 2010
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Point still stands, unless you have density and electrostatic performance for both Intel 10nm+ and TSMC N7.
On density at least we have a pretty good idea though... Intel's 10 is 54x36 whereas TSMC 7 is 54x40. So yeah it's pretty close.
 

IntelUser2000

Elite Member
Oct 14, 2003
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Are they going to still use 4-way SMT on Xeon H?
There should be no need to, unless Icelake uarch supports 4-way SMT. As it says, Xeon H is just Icelake with more cores on an MCM and lower clock.

I find Xeon H questionable. They are saying it'll clock 30% lower, so the 44 core will end up only being 40% faster than 24 core Icelake Xeon. It's reasonable to assume Xeon H supports VNNI instructions for double NN performance, and regular Xeon doesn't. Aside from that there's every reason to get a regular Xeon.

Unless Xeon H uses less power and costs less than regular Xeon, just like Xeon Phi.

Icelake SP to offer 38cores, 8channel memory, 32gb of HBM2 at 650gb/s
While I find use of HBM2 exciting and a confirmation of PCWatch article saying HBM was Intel's original plan, I am little puzzled by the amount of cores.

By this point they must be aware of a future 64 core EPYC. Since the top end 28 core Xeon SP is ~10% faster than 32 core EPYC, a 38 core Icelake Xeon, we have to assume if they want it to be merely on par with EPYC, it needs to have per core performance ~33% faster than Skylake-SP. Or 50% if they want 10% advantage to stay.
 
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IntelUser2000

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I think Xeon Phi was a victim of process delays.

Originally they wanted Knights Landing version of Phi to be out in 2015. Not only that it had better specs and used less power. It was delayed nearly a year. I think a mid 2017 intro for 10nm Knights Hill would have been feasible, best-case.

Then the timeframe probably shifted to mid 2018, before the 10nm delay. Before the cancellation Knights Hill was planned for mid 2019. Now they are forced to use Knights Mill, a 14nm part for 2018.

Mid 2017 would have made Knights Hill likely competitive with Nvidia parts. Mid 2018 not so much, but it might have justified continual development. Coming in Mid 2019, it probably made sense to replace it with a souped-up Xeon.
 

jpiniero

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Oct 1, 2010
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By this point they must be aware of a future 64 core EPYC. Since the top end 28 core Xeon SP is ~10% faster than 32 core EPYC, a 38 core Icelake Xeon, we have to assume if they want it to be merely on par with EPYC, it needs to have per core performance ~33% faster than Skylake-SP. Or 50% if they want 10% advantage to stay.
The worst part of it is that this sounds like it's still monolithic. Assuming it is, given the 10 nm yield issues the earliest they could release this is the end of 2019... but it's probably more like 2020. We'll have to see.

The HBM2 makes it sound like they are doubling down on HPC... and hoping that their marketing team can work their magic on the rest of the market.
 

IntelUser2000

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Oct 14, 2003
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The HBM2 makes it sound like they are doubling down on HPC... and hoping that their marketing team can work their magic on the rest of the market.
Marketing teams are more effective on client than server, because more informed decisions are made. Plus its an area where performance is still demanded. So if they lose the technical advantage they'll lose marketshare fast.
 
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jpiniero

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Oct 1, 2010
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Are they going to still use 4-way SMT on Xeon H?
One idea would be if Icelake supports MorphCore, they could throw an additional two AVX-512 units onto the Xeon H. At 2 Ghz and 44 cores, the Xeon H would have 5.6 DP TFlops, which in 2020 wouldn't really be competitive but not being competitive hasn't stopped Intel from getting HPC deals either.
 

raghu78

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Aug 23, 2012
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The worst part of it is that this sounds like it's still monolithic. Assuming it is, given the 10 nm yield issues the earliest they could release this is the end of 2019... but it's probably more like 2020. We'll have to see.

The HBM2 makes it sound like they are doubling down on HPC... and hoping that their marketing team can work their magic on the rest of the market.
Yes the problem for Intel is Icelake-SP is still monolithic and given their 10nm yield issues getting this part out in H2 2019 with good yields is going to be a challenge given that Intel is struggling to yield 70 sq mm Cannonlake chips and the high volume availability of CNL is now pushed to H2 2018. The other major problem for Intel is the GF 7SoC process with 6T libraries has sufficient performance to power 3.5 Ghz designs whereas 14LPP needed 9T libraries for hitting > 3 Ghz. Those clocks are more than enough for servers and thats why Rome is likely being built at 7SoC to maximize density and power efficiency.

https://www.semiwiki.com/forum/content/6879-exclusive-globalfoundries-discloses-7nm-process-detail.html

Here are the key specs
Intel 10nm

CPP = 54nm
MMP = 36nm
Tracks -7.56
Cell area = CPP x MMP x Tracks = 54 x 36 x 7.56 = 14697 sq nm

6transistor HD SRAM cell = 0.0312 sq um

GF 7SoC

CPP = 56nm
MMP = 40nm
Tracks -6
Cell area = CPP x MMP x Tracks = 56 x 36 x 7.56 = 13440 sq nm

6transistor HD SRAM cell = 0.0269 sq um

GF 7SoC cell area is 91% of Intel 10nm and HD SRAM cell is 86% of Intel 10nm. In comparison Intel 14nm vs GF 14LPP was very favourable for Intel.

https://www.semiwiki.com/forum/content/6713-14nm-16nm-10nm-7nm-what-we-know-now.html
https://www.pcper.com/news/Processors/AMD-Details-Zen-ISCCC
https://pc.watch.impress.co.jp/img/pcw/docs/733/713/html/9.jpg.html

Intel 14nm

CPP = 70nm
MMP = 52nm
Tracks -7.67
Cell area = CPP x MMP x Tracks = 54 x 36 x 7.56 = 27919 sq nm

6transistor HD SRAM cell = 0.058sq um

GF 14LPP High Density

CPP = 78nm
MMP = 64nm
Tracks - 9
Cell area = CPP x MMP x Tracks = 78 x 64 x 9 = 44928 sq nm

6transistor HD SRAM cell = 0.080 sq um

Intel is walking into a perfect storm where their process node lead has now turned into a deficit and AMD has a solid quad MCM implementation working while Intel is still stuck with monolithic die and has to wait till Sapphire Rapids for chiplets with EMIB. Thats why AMD can go for 64C and 256 MB L3 cache with 7nm Rome. AMD will still have die size around 200 sq mm given the massive shrink in logic (13440/44928 = 0.299) and HD SRAM (0.0269 / 0.080 = 0.336) . AMD is getting more than 1.5 full node shrink from 14LPP 9T to 7SoC 6T. Intel meanwhile is getting just about a full node shrink (14697/27919 = 0.52) with HD SRAM (0.0312/0.058 = 0.53). 2019 could bring huge disruption to x86 server market if AMD and GF can deliver on 7nm Rome.
 

Dayman1225

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Aug 14, 2017
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