Intel is now targeting performance improvements, power reductions & area shrinks in successive 10nm nodes. New ball game for Intel. Intel is now behaving more like the pure fabs with incremental improvements. Interesting times - Intel needs EMIB yesterday!
I'm sure the majority of you all have already seen this from the Coffee Lake thread - but I thought it was appropriate to post it here
Intel will have better performance and TSMC better density - if history is any guide. ARM just doesn't need Intel's better parametric performance right now. It also seems really difficult for Intel to offer good pricing to designers even at lower densities. The integrated designer/fab model is Intel's strength in x86 and weakness in everything else.It's horrible because TSMC is going HVM with their 7nm SoC node like half a year earlier.
That's not how you get design wins.
We don't know anything about Intel's 7nm yet. My comment was based on history - there is no factual basis for making what you claim now - except, obviously, the 'earlier' part.It's neither actually. N7 is better AND earlier.
Yes. For a comparison of Intel 10nm vs TSMC N7 vs GF 7LPIs this contacted gate pitch times metal pitch?
Thanks!Yes. For a comparison of Intel 10nm vs TSMC N7 vs GF 7LP
There should be no need to, unless Icelake uarch supports 4-way SMT. As it says, Xeon H is just Icelake with more cores on an MCM and lower clock.Are they going to still use 4-way SMT on Xeon H?
While I find use of HBM2 exciting and a confirmation of PCWatch article saying HBM was Intel's original plan, I am little puzzled by the amount of cores.Icelake SP to offer 38cores, 8channel memory, 32gb of HBM2 at 650gb/s
The worst part of it is that this sounds like it's still monolithic. Assuming it is, given the 10 nm yield issues the earliest they could release this is the end of 2019... but it's probably more like 2020. We'll have to see.By this point they must be aware of a future 64 core EPYC. Since the top end 28 core Xeon SP is ~10% faster than 32 core EPYC, a 38 core Icelake Xeon, we have to assume if they want it to be merely on par with EPYC, it needs to have per core performance ~33% faster than Skylake-SP. Or 50% if they want 10% advantage to stay.
Marketing teams are more effective on client than server, because more informed decisions are made. Plus its an area where performance is still demanded. So if they lose the technical advantage they'll lose marketshare fast.The HBM2 makes it sound like they are doubling down on HPC... and hoping that their marketing team can work their magic on the rest of the market.
One idea would be if Icelake supports MorphCore, they could throw an additional two AVX-512 units onto the Xeon H. At 2 Ghz and 44 cores, the Xeon H would have 5.6 DP TFlops, which in 2020 wouldn't really be competitive but not being competitive hasn't stopped Intel from getting HPC deals either.Are they going to still use 4-way SMT on Xeon H?
Yes the problem for Intel is Icelake-SP is still monolithic and given their 10nm yield issues getting this part out in H2 2019 with good yields is going to be a challenge given that Intel is struggling to yield 70 sq mm Cannonlake chips and the high volume availability of CNL is now pushed to H2 2018. The other major problem for Intel is the GF 7SoC process with 6T libraries has sufficient performance to power 3.5 Ghz designs whereas 14LPP needed 9T libraries for hitting > 3 Ghz. Those clocks are more than enough for servers and thats why Rome is likely being built at 7SoC to maximize density and power efficiency.The worst part of it is that this sounds like it's still monolithic. Assuming it is, given the 10 nm yield issues the earliest they could release this is the end of 2019... but it's probably more like 2020. We'll have to see.
The HBM2 makes it sound like they are doubling down on HPC... and hoping that their marketing team can work their magic on the rest of the market.
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