Discussion Intel current and future Lakes & Rapids thread

[mohit9206]

Ice Lake is a new architecture, bringing the first meaningful IPC increase since Skylake in 2015. Note that according to slides from Intel manufacturing day, 10 nm + has less "transistor performance" than 14 nm ++, which may manifest as slightly reduced peak overclock.

There was a Cannon Lake-S (for desktops) 8-core in the works, before it was cancelled and replaced by Coffee Lake 6-core. Ice Lake is an opportunity to realize the 8-core.

Use fast storage? Possibly PCI Express 4.0 to buff the DMI link.

Use integrated GPUs? Cannon Lake has Gen 10, and possibly more cores: 320-384 cores (40-48 EUs) in GT2. Ice Lake Gen 11 is likely to build on that.

Ice lake Gen 11 gpu may be able to compete with Raven Ridge iGPU if Intel makes some significant advancements. However it is still disappointing that igpu performance is still very low. It was predicted a few years ago that igpu will replace low end sub $100 graphics but that hasn't been the case.

 

[nvgpu]

 

[IntelUser2000]

Ice lake Gen 11 gpu may be able to compete with Raven Ridge iGPU if Intel makes some significant advancements.

AMD claims only 40% gain over current generation. Iris generation based on Coffelake would be enough. On mobile the performance of HD 620 is on par with Radeon iGPU.

Unfortunately it doesn't seem like Cannonlake will bring much in terms of performance. For GT2 parts they'll have to wait for Icelake.

However it is still disappointing that igpu performance is still very low. It was predicted a few years ago that igpu will replace low end sub $100 graphics but that hasn't been the case.

Yea... It's based on the same prediction that we would be reaching Singularity by 2050, or anyone seriously believing Elon Musk's claims AI will be a significant threat to us in 20 years. Or more realistically, the expectation that 1 EFLOPs @ 20MW would have been achievable by 2018.

All of those predictions nearly single-handedly hinged on Moore's Law progressing at up-to-the-late-1990s level.

On computers the performance is being segmented by how much power the chip can use, how much die space it is using, and how much it costs. Of course, there's also how well the company executes their plans. That means iGPUs will be naturally be significantly(I mean 1/3rd or less) slower than discrete graphics.

Now, I do not believe the advancement would stop. It would just slow to a point where it would be like rest of the non-computer technology world.

 

[Dayman1225]

AMD are claiming that an EPYC die costs 59% of a monolithic die, I wonder how much EMIB would reduce cost for Intel.

 

[Ajay]

AMD are claiming that an EPYC die costs 59% of a monolithic die, I wonder how much EMIB would reduce cost for Intel.

Dayman, this is an Intel thread. Wondering about the costs savings from EMIB is one thing, posting a big graphic on Ryzen is off topic really.

 

[IEC]

Wondering about the costs savings from EMIB is one thing, posting a big graphic on Ryzen is off topic really.

It'll be interesting to see how Intel's EMIB plays out. I would think the tradeoffs made would be very similar to what AMD has done... which would be ideal for everyone from a software optimization standpoint, at least.

 

[Bouowmx]

Revisiting Cascade Lake. Current Skylake-SP 3x4 mesh (10 cores) is measured 308 mm², and 5x6 mesh (28 cores) is estimated to be 677 mm². See: http://www.anandtech.com/show/11550...-core-i9-7900x-i7-7820x-and-i7-7800x-tested/6

Even more cores for > 700 mm² (like a 6x6 mesh with 34 cores)?

 

[Dayman1225]

Dayman, this is an Intel thread. Wondering about the costs savings from EMIB is one thing, posting a big graphic on Ryzen is off topic really.

Fair enough!

 

[Arachnotronic]

Revisiting Cascade Lake. Current Skylake-SP 3x4 mesh (10 cores) is measured 308 mm², and 5x6 mesh (28 cores) is estimated to be 677 mm². See: http://www.anandtech.com/show/11550...-core-i9-7900x-i7-7820x-and-i7-7800x-tested/6

Even more cores for > 700 mm² (like a 6x6 mesh with 34 cores)?

I think they will add another row of cores on each chip for Cascade Lake, yeah. New process + physical implementation improvements should allow them to pull it off w/o much regression in frequency.

 

[jpiniero]

I think they will add another row of cores on each chip for Cascade Lake, yeah. New process + physical implementation improvements should allow them to pull it off w/o much regression in frequency.

I don't think so, I think it'll be clock speed only. The dies are big enough as it is... It's not like yield is going to be any better.

 

[IntelUser2000]

I don't think so, I think it'll be clock speed only. The dies are big enough as it is... It's not like yield is going to be any better.

I think it can go either way. I am more leaning towards same amount of cores though.

It still can be a nice platform. They might enable the LSD back and improve performance and power usage. As a platform it'll bring Optane DIMM support and variants of the chips with FPGA on the same package. As for Optane some server systems say it's ready for it.

 

[Dayman1225]

Hot Chips 2017: Intel Deep Dives Into EMIB:
http://www.tomshardware.com/news/intel-emib-interconnect-fpga-chiplet,35316.html

 

[IntelUser2000]

AMD are claiming that an EPYC die costs 59% of a monolithic die, I wonder how much EMIB would reduce cost for Intel.

It is an extremely simplified view. At the same die size, monolithic die would be cheaper in terms of packaging. So die size wise it may be at 0.59x, but total costs might be higher. Monolithic is also better in terms of absolute performance.

EMIB isn't necessarily about cost. Cost-wise from most expensive to least expensive:

Interposer-EMIB-MCM

The problem with MCM is that it doesn't provide a lot of bandwidth between the dies. EMIB is cheaper than Interposer but more expensive than MCM. EMIB is a cheaper solution among high-banwidth connections.*

Intel stated the reason they want to go the EMIB route is because due to difficulties of using huge monolithic dies on brand spanking new process, but they could go with a much smaller multi-die with EMIB connections.

*eDRAM on Iris chips use MCM not EMIB or Interposers.

 

[DrMrLordX]

I'm curious as to how EMIB will handle signal routing between dice that are not connected directly.

 

[jpiniero]

Intel stated the reason they want to go the EMIB route is because due to difficulties of using huge monolithic dies on brand spanking new process, but they could go with a much smaller multi-die with EMIB connections.

Difficulty is understating it really. I'm convinced that Intel can't/won't release a 10 nm product of a decent size and 7 nm will be that much worse.

I'm curious as to how EMIB will handle signal routing between dice that are not connected directly.

The Mesh.

 

[DrMrLordX]

The Mesh.

So does that mean there are transistors baked into each die that permit signal routing across the die?

 

[Ajay]

So does that mean there are transistors baked into each die that permit signal routing across the die?

Whatever the phy and protocol are, there would need to be some logic and a some power circuits to drive the signal for each connection.

 

[DrMrLordX]

Whatever the phy and protocol are, there would need to be some logic and a some power circuits to drive the signal for each connection.

So you would have to alter the die itself to make use of EMIB. I would think with an interposer, that might not be the case.

 

[Arachnotronic]

So you would have to alter the die itself to make use of EMIB. I would think with an interposer, that might not be the case.

You have to design your silicon to work with an interposer, too. You can't just stick any old chip onto an interposer and have it talk to other chips on the package.

 

[DrMrLordX]

You have to design your silicon to work with an interposer, too. You can't just stick any old chip onto an interposer and have it talk to other chips on the package.

Well uh, why not? Could you not take . . . let's say, a Broadwell-C die and the Crystal Well die and replace the MCM interface with an interposer? Without fundamentally changing either die?

 

[Ajay]

Well uh, why not? Could you not take . . . let's say, a Broadwell-C die and the Crystal Well die and replace the MCM interface with an interposer? Without fundamentally changing either die?

You need 1) A proper communication protocol that each modular chip understands and 2) you need to push high drive currents (and probably lower frequencies) for the off chip traces.

 

[DrMrLordX]

You need 1) A proper communication protocol that each modular chip understands and 2) you need to push high drive currents (and probably lower frequencies) for the off chip traces.

Right. So you can't achieve that when moving both dice to an interposer?

 

[IntelUser2000]

So you would have to alter the die itself to make use of EMIB. I would think with an interposer, that might not be the case.

It doesn't sound like the AIB/UIB chiplets are additional to the controllers, rather replace them. In that case its the same with Interposer solutions needing HBM controller on-die.

 

[AtenRa]

AMD claims only 40% gain over current generation. Iris generation based on Coffelake would be enough.

40% at half the TDP, that means 40% higher performance than 35W TDP Bristol Ridge at 15W TDP.

On mobile the performance of HD 620 is on par with Radeon iGPU.

That is not true, even the 384 Shader on the A12-9700p 15W TDP is way faster than 15W TDP HD620. Go to Notebookcheck and compare 15W A12-9700p to HD620 like the Core i7 7500U.
When Bristol Ridge is not CPU limited at low resolutions the AMD iGPU is a lot faster than HD620.

 

[Ajay]

Right. So you can't achieve that when moving both dice to an interposer?

Not without pre-planning. You have to design for modularity and inter-chip connectivity.