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Discussion Intel current and future Lakes & Rapids thread

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AtenRa said:
That is not true, even the 384 Shader on the A12-9700p 15W TDP is way faster than 15W TDP HD620. Go to Notebookcheck and compare 15W A12-9700p to HD620 like the Core i7 7500U.
When Bristol Ridge is not CPU limited at low resolutions the AMD iGPU is a lot faster than HD620.
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Bristol Ridge throttles like mad at 15 W in actual titles, that's why it ends up slower than the 620.
 
Glo. said:
When can we expect launch of Ice Lake CPUs for desktop?
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2H18 according to Ashraf: https://www.fool.com/investing/2017/07/30/intel-corporation-hints-at-ice-lake-launch-in-mid.aspx
But it's not 100% solid yet:
TMFChipFool* said:
Although I might be reading too much into this, I think these comments strongly suggest that Intel plans to launch products based on its second-generation 10nm architecture, known as Ice Lake, in the second half of 2018.
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EDIT 2H18, not 1H do'h!
 
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jpiniero said:
I would think it would have been released by now if they were planning on doing it. Coffee Lake I suppose could happen instead.
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You seem to be under the impression that Xeon D is more important than Intel's other product lines. It really isn't, it's far less important than Xeon Scalable or the Core PC products.
 
Arachnotronic said:
Agreed, Q4 2018 would be nice and is probably realistic -- a year after CFL-S. I can't see CFL-S lasting less than a year.
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The question is not about CFL-S lasting more than a year but whether 10+ will be in good shape by Q3 2018 to ramp Icelake in high volume. Skylake launched in Aug 2015 and Kabylake launched in Jan 2017. So a greater than 1 year gap between two successive generation is not something new.
 
What is Xeon D's use case? Middle-cost, compared to Goldmont below, and Skylake-SP and W above? Not sure: they exist, but not a lot of discussion about it.
 
Arachnotronic said:
You seem to be under the impression that Xeon D is more important than Intel's other product lines. It really isn't, it's far less important than Xeon Scalable or the Core PC products.
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Oh, it's extremely important now.. especially since that they wasted all that space on AVX-512 on the SP line and that's not going to be fixable for some time.
 
jpiniero said:
Oh, it's extremely important now.. especially since that they wasted all that space on AVX-512 on the SP line and that's not going to be fixable for some time.
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I'm glad they got it done already and I hope they don't fix it. Now at die shrink time, and in the future, they've already done it once.
 
Since desktop apparently is an afterthought now, I'm definitely getting CLF (unless ST performance and real clocks are lower than SKL/KBL). I'm not prepared to sit around until 2H2018 only to find out that apparently IL was delayed or simply silence about the desktop version.
 
jpiniero said:
Oh, it's extremely important now.. especially since that they wasted all that space on AVX-512 on the SP line and that's not going to be fixable for some time.
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10nm will fix the the die usage problem - and go along way to bringing the heat under control. Ice Lake SP should deliver on AVX-512 and higher core counts. I do wonder if Intel will be buffing out the L2 some more (VM oriented design - boo hoo).
 
Ajay said:
10nm will fix the the die usage problem - and go along way to bringing the heat under control. Ice Lake SP should deliver on AVX-512 and higher core counts. I do wonder if Intel will be buffing out the L2 some more (VM oriented design - boo hoo).
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It's still going to be a problem since the additional unit is taking up space that could be used for cores.
 
Or more GPU, or flat out cheaper chips, or.....

From the little I've seen so far it is looking something of a questionable feature overall. Have to presume Intel know of some markets where its a good idea though. They do know what they're doing by and large 🙂
 
Ajay said:
10nm will fix the the die usage problem - and go along way to bringing the heat under control. Ice Lake SP should deliver on AVX-512 and higher core counts. I do wonder if Intel will be buffing out the L2 some more (VM oriented design - boo hoo).
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I think so, too. Over time I also could see Intel sharing an L2 cache between core pairs, C2D style. This would allow Intel to do targeted SKUs that have 2X the L2 cache/core by disabling one of the cores in each core pair.

Lots of possibilities with the move to 10nm and the shift to server-specific architectures and client specific architectures.
 
Arachnotronic said:
"Wasted" space? How so?
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For starters they had to scale back the core count, and also gimped the L3 to make room for it. It hurts the competitiveness. It especially looks real bad now because they jacked up prices with the SP line and yet will have to slash it soon because of Epyc.
 
jpiniero said:
For starters they had to scale back the core count, and also gimped the L3 to make room for it. It hurts the competitiveness. It especially looks real bad now because they jacked up prices with the SP line and yet will have to slash it soon because of Epyc.
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Scaled back core count but they added the benefit of AVX-512, which should be pretty broadly used in the data center market.

About the "jacked up prices," those are fantasy numbers that no major CPU buyer is going to pay close to.

The L3 on the new CPUs is a step back, yeah -- higher latency in clocks, lower clocks, and it's a victim cache. But I'm not sure it was reworked like this because of the AVX512 units. Probably more because they beefed up the L2 per core and sticking with the old cache structure would've taken up a lot of die space.
 
Arachnotronic said:
The L3 on the new CPUs is a step back, yeah -- higher latency in clocks, lower clocks, and it's a victim cache. But I'm not sure it was reworked like this because of the AVX512 units. Probably more because they beefed up the L2 per core and sticking with the old cache structure would've taken up a lot of die space.
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I know its apples and oranges, but didn't Apple move to a full L3 victim cache on their A9 and A10 cpus? Personally, with a large L2 cache, I don't really see the downside to a L3 victim cache.

Now the smaller size, higher latency, lower clocks does impact performance.
 
Bouowmx said:
What is Xeon D's use case? Middle-cost, compared to Goldmont below, and Skylake-SP and W above? Not sure: they exist, but not a lot of discussion about it.
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Sorry to attempt an answer at this late, but it looked like everyone ignored your inquiry.

Intel seems to have positioned Xeon D as a low-power server/workstation blade CPU. It appears to be overall the most efficient lineup of Xeon processors available. Or at least it was when it launched, and it remained so when Intel started showing off Denverton as well. Not really sure how Broadwell-based Xeon-D fares against Skylake-based Xeon in terms of raw efficiency.

The downside to Xeon D is that it has to remain within a fairly low clockspeed envelope - generally below 3 GHz - to meet power targets. So it's not well-suited to applications that require high individual core performance (low-latency VMs, etc).

Near as I can tell, Intel's general "professional" CPU stack goes a bit like this:

Denverton - network appliances and suchlike
Xeon-D - low-power perf/watt applications, preferably those that are highly-scalable with core/thread count.
Xeon - everything else
 
DrMrLordX said:
Denverton - network appliances and suchlike
Xeon-D - low-power perf/watt applications, preferably those that are highly-scalable with core/thread count.
Xeon - everything else
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Xeon D is also for network appliances. It was a result of collaboration with Facebook, and an answer to ARM servers being used in low compute but high networking requirement. Their chips are quite widely used in software router/switch applications for ISPs but they needed a more purpose built SoC that could also go in cheaper and lower cost/power devices.

The Atom based ones are there to fill the even lower end of the segment.

What is Xeon D's use case? Middle-cost, compared to Goldmont below, and Skylake-SP and W above? Not sure: they exist, but not a lot of discussion about it.
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Back before the software router/switch was popular they started offering Xeon platforms with QAT and other features on the chipset that's more suited for networking appliances.

The large cores though are used in more broad usage scenarios where other types of applications can be run in addition to software networking. In the case where a more purpose-built networking chips are needed the regular Xeon chips weren't as suited. The answer became Xeon D. The server market isn't so simple as to think there's just one type of usage. It's as varied as any market.
 
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