- Mar 10, 2006
They had been using a victim cache since the A7. The A9X did away with the L3 though and the A10X kept the L3 off and saw a big jump in L2 cache size (from 3MB to 8MB), which helped boost perf/clock a lot.I know its apples and oranges, but didn't Apple move to a full L3 victim cache on their A9 and A10 cpus? Personally, with a large L2 cache, I don't really see the downside to a L3 victim cache.
Now the smaller size, higher latency, lower clocks does impact performance.
For a client design you really want a big, fast, low-latency cache shared among your cores, and that's why you see Intel with Gemini Lake moving from 1MB/core pair in Apollo Lake to 4MB/quad core cluster. In a single-thread scenario, your core has access to a big pile of L2, and even when all four cores are loaded up, they have access to a large L2 pool.
I would like to see Intel diverge their cores significantly -- Atom for lower-end client/IoTG/etc., Core for high-end client, and then a separate core design for Xeon.
By trying to "converge" the cores to save on some R&D spending, Intel makes trade-offs that are annoying