• Guest, The rules for the P & N subforum have been updated to prohibit "ad hominem" or personal attacks against other posters. See the full details in the post "Politics and News Rules & Guidelines."

Discussion Intel current and future Lakes & Rapids thread

Page 15 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

TheF34RChannel

Senior member
May 18, 2017
786
306
136
Wait for Ice Lake-S 8-core? 2017 is the year of waiting :D. I realize that 6 to 8 is a smaller relative jump than 4 to 6, but still.

By some divine intervention, I was wise enough to get into gaming by pimping an used Sandy Bridge computer and getting NVIDIA Pascal in 2016?
Ha ha ha! I'm getting a 8700K and then an 8C Tiger Lake-S or maybe even skip that. And a 2080 Volta, I'll get that too.

Are you asking or telling? Good choice though, although that CPU generation is beginning to show its age. So what are you in the market for?
 

Bouowmx

Golden Member
Nov 13, 2016
1,133
545
146
I think I'm settling when Intel stops increasing core count in the -S series. Ice Lake 8-core feels like that point. Unless Tiger Lake-S has a 10-core :eek:.

As for NVIDIA Volta, might be skipping GeForce GTX 2070 because of CPU bottleneck (144 Hz).

So waiting intensifies..
 

TheF34RChannel

Senior member
May 18, 2017
786
306
136
They'll leave it at 8 for a while I suspect. But who knows...

Do you expect much of a bottleneck @ 144Hz with the new CPUs? We should be alright for a little while longer, although we certainly are approaching the moment where current CPU architectures strangle near future GPU architectures (Nvidia its Tom something discussed this recently as well in a PCPER video) - the CPU as we know it drastically needs improving, instead of small incremental upgrades. For Intel, via Sapphire Rapid maybe...? If we get a mainstream part to begin with?
 

mikk

Diamond Member
May 15, 2012
3,287
1,093
136
They have a development platform by this time already, that's encouraging.
 

Bouowmx

Golden Member
Nov 13, 2016
1,133
545
146
Ice Lake timeliness is promising. Ice Lake architecture is unknown, but it's been in the works for a while; likely a refinement of Skylake, nothing drastic or revolutionary. Gen 11 graphics tho?
Looking forward to seeing Ice Lake-S 8-core in 2018 H2.
 
Mar 10, 2006
11,715
2,011
126
Ice Lake timeliness is promising. Ice Lake architecture is unknown, but it's been in the works for a while; likely a refinement of Skylake, nothing drastic or revolutionary. Gen 11 graphics tho?
Looking forward to seeing Ice Lake-S 8-core.
Ice Lake seems to have a bigger L1D cache, which could be indicative of bigger changes elsewhere in the core. You don't make changes to the L1D cache like that, esp. given how long Intel has stuck with that size, unless the rest of the machine would've been bottlenecked w/o the change, IMO.

Here are my predictions for the Ice Lake core changes:

- Increase the size of the uOp cache and allow for >6 uOps to be sent to the uOp queue from this cache per cycle.
- Widen decode; SKL can issue 5 uOps from the legacy decode pipeline (it uses 4 hardware decoders but with "tricks" to get a peak of 5 uOps), but I think they'll add an additional decoder.
- To take advantage of wider instruction supply in the front end, I expect Intel to go from an 8-wide backend to a 10-wide backend (similar to Zen), though I'd expect the schedule to remain unified rather than a split Int/FP as in the Zen uArch.
- A return to an 8-way associative L2 cache. Intel says that they saved power by going from 8-way to 4-way and this also helped with SKX (allowing the 768KB cache to be "tacked on" more easily), and they even claim no perf hit, but I think that this is wrong and it's part of the reason why SKL-S did not deliver more IPC over BDW client than it really should've (Intel seems to have been aiming for 10-15% based on the increases in the various OoO structures). With 10nm+ power consumption should come down a lot allowing for the higher cache associativity (increased hit rate in the L2 cache).
- Standard 10-15% increases in the sizes of the various buffers (OoO window, in-flight loads/stores, scheduler size, PRF sizes, and allocation queue).
 

imported_bman

Senior member
Jul 29, 2007
262
54
101
Do you think we will get a 400-series PCH with Icelake that enables a new PCIe topology (4x NVMe lanes direct to the CPU) and maybe PCIe 4.0.
 
Mar 10, 2006
11,715
2,011
126
Do you think we will get a 400-series PCH with Icelake that enables a new PCIe topology (4x NVMe lanes direct to the CPU) and maybe PCIe 4.0.
I think we'll get a new PCH, for sure, but as to what features it has? No idea.

10nm does bring a big density improvement, so it'd be a shame not to spend those extra xtors on something like that.
 
  • Like
Reactions: imported_bman

IntelUser2000

Elite Member
Oct 14, 2003
7,626
2,518
136
Do you think we will get a 400-series PCH with Icelake that enables a new PCIe topology (4x NVMe lanes direct to the CPU) and maybe PCIe 4.0.
PCIe 4.0 - Yes. The specification was set in stone July of this year. PCIe 3.0 took ~1 year before it showed up in products, so Icelake having PCIe 4.0 support is good as any.

Probably 4x NVMe lanes from the CPU too. Although I think this could depend just as much on their decision to segment it from the HEDT line.

I think the factor that complicates whether we'll see a 400-series PCH is whether it'll finally come on-die or not. From the viewpoint of keeping it separate to keep older fabs utilized and to reduce recalls their decision to keep it separate makes sense.

From a competitive standpoint it does not. Having the PCH integrated seems to be the key to reduce Core platform idle power competitive with Atom/ARM platforms. Having platform power twice the level of competition is simply not acceptable in this day and age, especially when certain low power platforms like Apple chips already reach Intel chips in the performance level. Integrating the PCH would not only reduce TDP because it'll cut down on external interconnects that use power and move the components to a new process, power states can be transitioned faster meaning better power management during actual use.

I wouldn't be entirely surprised if we see a 400-series chipset, though. The reason is that 300-series chipset integrates WiFi and only needs PHY to make it work. If they get the chipset integrated on-die that would be a big deal since it would be the second chip only to Geminilake to having on-die WiFi. Due to signalling requirements on-die WiFi has not been possible though many years ago Intel showed a research chip that has on-die WiFi: https://www.theverge.com/2012/2/19/2810041/intel-rosepoint-atom-wi-fi-integrated

If they can integrate the PCH in the Icelake generation we'd see a substantial improvement for Icelake generation PCs even if the CPU itself doesn't bring much. If its not going to be on-die on Icelake we'll likely only see it post-Tigerlake.

A return to an 8-way associative L2 cache.
Whether this will happen IMO depends on what they want to do with the server line. If they do the same thing as they did with Skylake-SP, I don't think we'll see 8-way L2 cache. If a 256KB L2 cache is at 8-way a 1MB L2 cache needs to be 32-way. Do they see a need to do so? Sure they can keep the L2 cache design different but that means more design work. The fact that they call Skylake-SP a big change despite what sounds like to layman a small change(mesh/AVX512/Cache) is an evidence how complex CPUs are nowadays.
 

Bouowmx

Golden Member
Nov 13, 2016
1,133
545
146
Confirm if I have Intel schedule correct:

2017 H1: 14 nm +, Kaby Lake client, Skylake-SP/X
2017 H2: 14 nm ++, Coffee Lake client
2017 Q4-2018 Q1: 10 nm, Cannon Lake mobile
2018 H1: 14 nm ++, Coffee Lake-SP/X (Skylake-SP/X optimized)
2018 H2: 10 nm +, Ice Lake client

Seems pretty consistent so far. However, 10 nm ++ marks data-center first (and client second). Does that mean:
2019 H1: 10 nm +, Ice Lake-SP/X, and a short time later..
2019 H2: 10 nm ++, Tiger Lake-SP/X
2020 H1: 10 nm ++, Tiger Lake client
2020 H2: 7 nm, data center
 

french toast

Senior member
Feb 22, 2017
988
824
136
Bth Intel and AMD have to go wider pretty soon I would think/hope, clock improvements from process are going to hit a wall if not already, but process still scales well with power savings and density.
I either one with icelake or zen2 does not take the opportunity to go wider they might regret it in a couple of years.

What is the chance that icelake goes much wider and introduces 4x SMT? That would suit their 10nm process better would it not?
 

Bouowmx

Golden Member
Nov 13, 2016
1,133
545
146
Not remembering Cascade Lake, I intended Coffee Lake-SP/X to represent Skylake-SP/X and Kaby Lake-X optimized in 14 nm ++.

4 threads/core is in Xeon Phi, might end up in Ice Lake-SP/X if it is added.

Cannon Lake GPU EU count has been a while ago. Anybody care to put me up-to-speed concerning that topic? Last time I remembered is 48 EUs (384 cores), at 1 GHz, is GT2: https://forums.anandtech.com/threads/intel-skylake-kaby-lake-coffee-lake-thread-coffee-lake-s-specs-out-page-554.2428363/page-388#post-38836966 . 48 EUs in Cannon Lake GT2 might also mean 48 EUs in Ice Lake GT2.

Curiously, I discovered Intel GPUs (Gen 9) can do half-precision at 2/1 rate, and double-precision at 1/4 rate of single-precision. Tangentially, half-precision in games is a topic that AMD Vega revived.
 
  • Like
Reactions: psolord

imported_bman

Senior member
Jul 29, 2007
262
54
101
802.11ax looks nice, but 802.11ay looks like the game changer to me assuming MU-MIMO helps significantly with attenuation. Being able to connect a laptop to a display without wires while using a visually lossless codec would be really slick.
 
Last edited:
  • Like
Reactions: Arachnotronic

IntelUser2000

Elite Member
Oct 14, 2003
7,626
2,518
136
Confirm if I have Intel schedule correct:

2017 H1: 14 nm +, Kaby Lake client, Skylake-SP/X
2017 H2: 14 nm ++, Coffee Lake client
2017 Q4-2018 Q1: 10 nm, Cannon Lake mobile
2018 H1: 14 nm ++, Coffee Lake-SP/X (Skylake-SP/X optimized)
2018 H2: 10 nm +, Ice Lake client

Seems pretty consistent so far. However, 10 nm ++ marks data-center first (and client second). Does that mean:

2019 H1: 10 nm +, Ice Lake-SP/X, and a short time later..
2019 H2: 10 nm ++, Tiger Lake-SP/X
2020 H1: 10 nm ++, Tiger Lake client
2020 H2: 7 nm, data center
Bold: They wouldn't do that, unless it exists together as with Coffeelake/Kabylake/Cannonlake. Minimum 1 year has to exist between replacements.

Next year we know that its

2018 H1: Cascade Lake

On consumer it should be
2019 H2: 10nm++, Tiger Lake

Which would make server
2019 H1: 10nm++

For 10nm++ we know the core will be based on Ice Lake: http://fs5.directupload.net/images/161229/9gxhy79y.png

Ice Lake "Refresh" means its the same Purley platform, but with Ice Lake CPUs. So for server it'll be Ice Lake, just on 10nm++.
 

eddman

Senior member
Dec 28, 2010
239
87
101
pc.watch.impress says Icelake is planned for 2018.
That's pretty much a given based on intel's own roadmap. Looks like late Q3, early Q4 for product launch, if things go right.

 
Last edited:

Bouowmx

Golden Member
Nov 13, 2016
1,133
545
146
"14 ++" is over 2016 H2, but we've yet to see a processor to implement it.

However, if Intel is aiming for yearly products, and Coffee Lake 14 nm ++ is in 2017 H2, Cannon Lake 10 nm in parallel by 2018 Q1, Ice Lake coming in 2018 H2 is sensible. Probably Q4. 10 nm readiness has yet to be proven.
 
  • Like
Reactions: beginner99

Ajay

Diamond Member
Jan 8, 2001
9,753
4,147
136
"14 ++" is over 2016 H2, but we've yet to see a processor to implement it.

However, if Intel is aiming for yearly products, and Coffee Lake 14 nm ++ is in 2017 H2, Cannon Lake 10 nm in parallel by 2018 Q1, Ice Lake coming in 2018 H2 is sensible. Probably Q4. 10 nm readiness has yet to be proven.
Process availability date plus verification = TTM (Time to Market).
 
  • Like
Reactions: IEC and Bouowmx

ASK THE COMMUNITY