Discussion Intel current and future Lakes & Rapids thread

[naukkis]

You got it backwards, 10nm designs could definitely be on 14nm, it's called backporting.

Silicon design could be easily ported to smaller process, but going backwards to bigger process is something that can be only possible if design isn't utilizing smaller process advantages at all. Natural evolution is to shrink previous node design to new node, and then evolve design to utilize transistors where smaller process makes it possible.

RocketLake isn't backported design but design made for 14nm, it is vastly different to Intel 10nm designs. CPU core might be closely related to 10nm versions but also it would need to be redesigned to 14nm, timings and layouts made for 10nm can't be used on 14nm.

Other way around things are easier and Intel could easily port eg Tigerlake to 7nm if desired - but to fully utilize 7nm possibilities need design made for 7nm - without backport opportunity.

 

[uzzi38]

Inspur CFO? They have no reason to bullshit a group of investors. They have no incentive to be pro intel or pro amd and they represent half the Chinese server market.Hard to see them getting Milan later than anyone else. But i guess because it's not super positive AMD news it must be wrong?

No, it's wrong because it's off by 2 quarters. Has nothing to do with being pro or anti AMD news.

Unless you want to provide some sort of public statement from Inspur backing up what you say they claim, then what you've said is as baseless as what I mentionned about a certain hyperscaler not even having an ICL-SP sample.

The only difference is that yours is less believable on top :^P

 

[Kuiva maa]

Zen + to Zen 2 was 15 months. So Zen 3 can still see an october launch and still be on cadence.

 

[FriedMoose]

Well, thats barely true today, and when Ryzen 3 comes out, most likely will not be true.

Only really because the majority of games are heavily GPU bound. A 9900K is 5-10% faster per clock than a 3700X in most games:

4GHz CPU Battle: Ryzen 3900X vs. 3700X vs. Core i9-9900K

Expanding upon all the testing we performed in our day-one 3rd-gen Ryzen coverage, today we'll be running a clock-for-clock comparison benchmark. IPC can be a good indicator...

www.techspot.com

An overclocked 9600K beats the 3900X in every single game Gamers Nexus tested, and the 10900K was 20% faster in the less GPU bound titles:

Intel Core i9-10900K CPU Review: Gaming, Overclocking, & Benchmarks vs. AMD Ryzen | GamersNexus

stub Intel’s continuing to bring the heat, literally and figuratively, and is now leveling its new 10C/20T part squarely at AMD. We have a separate in-depth review coming up on the 10600K, which has interesting implications for the R5 3600 and the realm of gaming, but for launch, we need to...

www.gamersnexus.net

I would expect Zen 3 to roughly match 10900K gaming performance and fall solidly behind Rocket Lake.

 

[liahos2]

No, it's wrong because it's off by 2 quarters. Has nothing to do with being pro or anti AMD news.

Unless you want to provide some sort of public statement from Inspur backing up what you say they claim, then what you've said is as baseless as what I mentionned about a certain hyperscaler not even having an ICL-SP sample.

The only difference is that yours is less believable on top :^P

Mizuho hosted the call (Analyst was Vijay Rakesh) with Inspur on 7/8. There isn't a transcript as far as I know but you can always call your mizuho rep!

 

[ajc9988]

Silicon design could be easily ported to smaller process, but going backwards to bigger process is something that can be only possible if design isn't utilizing smaller process advantages at all. Natural evolution is to shrink previous node design to new node, and then evolve design to utilize transistors where smaller process makes it possible.

RocketLake isn't backported design but design made for 14nm, it is vastly different to Intel 10nm designs. CPU core might be closely related to 10nm versions but also it would need to be redesigned to 14nm, timings and layouts made for 10nm can't be used on 14nm.

Other way around things are easier and Intel could easily port eg Tigerlake to 7nm if desired - but to fully utilize 7nm possibilities need design made for 7nm - without backport opportunity.

Not quite. So, usually designs made for smaller nodes are wider. The wider features help performance, but generate heat. The companies are using the efficiency in power consumption to lower heat with smaller nodes, thereby allowing the designs to work.

If you bring the design to a larger process, it now runs too hot. This is why Intel is said to be going to 8 cores instead of the current 10 cores. The changes also removed certain features so that instead of the 25% IPC tiger has over Skylake, you get about 20%.

So it really should be discussed in process node efficiencies as to why the redesign is needed going backwards, but not needed moving forwards.

But that is my take.

Can't say for sure if it is the local market price gouging or coming from AMD but the 3900XT is roughly $550 while the 3900X is going for roughly $470 so thats a $80 difference. If a 4900X now goes on the market for $550 it doesn't look like such a big price hike it really is.

They have done that every generation. I bought in for a 1950X. The price fell over time. The 2950X was $900 at launch or around that. The 3950X was mainstream and $750, which during the zen years, AMD process the quad channel memory and extra lanes at a $150 premium, so no discount there.

So if pricing is around the release price of the prior generation without going up, then it will be the same of what they have been doing.

The price increase argument is that they released XT to then say buy Zen 2 if you want cheaper and make Zen 3 way more than Zen 2 was at launch.

 

[dmens]

Silicon design could be easily ported to smaller process, but going backwards to bigger process is something that can be only possible if design isn't utilizing smaller process advantages at all.

Or, if they can't manufacture the smaller process. That's the joke.

 

[Dave2150]

Or, if they can't manufacture the smaller process. That's the joke.

Intel will be the last one laughing, when they eventually do roll out Alder Lake on 10nm+

 

[lobz]

Intel will be the last one laughing, when they eventually do roll out Alder Lake on 10nm+

You know this how?

 

[NostaSeronx]

Xeon/i7/i9 (Mobile) => Internal 7nm taped out
Xeon+Movidus => Internal 7nm taped out
Atom => Internal 7nm taped out
Atom+EyeQ => Internal 7nm taped out
Discrete Graphics (not-Ponte) => Internal 7nm taped out
NVM-3DXP (successor under the same name?) => Internal 7nm taped out

50,000-100,000 7nm wpm by 2H20-1Q21

As there is no issues on the 7nm node, Internal 5nm MassProd has been brought forward to 2022.

 

[Exist50]

Xeon/i7/i9 (Mobile) => Internal 7nm taped out
Xeon+Movidus => Internal 7nm taped out
Atom => Internal 7nm taped out
Atom+EyeQ => Internal 7nm taped out
Discrete Graphics (not-Ponte) => Internal 7nm taped out
NVM-3DXP (successor under the same name?) => Internal 7nm taped out

50,000-100,000 7nm wpm by 2H20-1Q21

As there is no issues on the 7nm node, Internal 5nm MassProd has been brought forward to 2022.

Can you please find a different place to troll?

 

[NostaSeronx]

Can you please find a different place to troll?

If you think that I am trolling, wow. 7nm will be a huge shock.

 

[CHADBOGA]

If you think that I am trolling, wow. 7nm will be a huge shock.

When will the first Intel products fabbed on their own 7nm process be out?

 

[NostaSeronx]

When will the first Intel products fabbed on their own 7nm process be out?

Client products launch first.

Calculate: 14nm Client to 14nm Server
Calculate: 10nm Client to 10nm Server
Conclusion Calc: Take the above then 7nm Client is that much earlier than 7nm Server. Find the 7nm Server product's launch year, subtract the previous differences.

10nm++ can also be 7nm; Basic feature converged core is 10++, Enhanced feature converged core is 7
10nm+++ can also be 7nm+; ' ' ' ' 10+++ ' ' ' 7+
// Core can be replaced with any IP (Core, Atom, Xe, etc)

 

[dmens]

Client products launch first.

Calculate: 14nm Client to 14nm Server
Calculate: 10nm Client to 10nm Server
Conclusion Calc: Take the above then 7nm Client is that much earlier than 7nm Server. Find the 7nm Server product's launch year, subtract the previous differences.

10nm++ can also be 7nm; Basic feature converged core is 10++, Enhanced feature converged core is 7
10nm+++ can also be 7nm+; ' ' ' ' 10+++ ' ' ' 7+
// Core can be replaced with any IP (Core, Atom, Xe, etc)

What are you smoking?

 

[NostaSeronx]

What are you smoking?

I am not. But, are you?
Intel has had NXE:3400B for sometime which in their words is enough for introduction[NPI Ramp]. They already have a plan to ramp with NXE:3400C which has higher uptimes. All the tools to get running with HVM will be at there places by 2H20/1Q21.

7nm NMOS and PMOS transistors types have the best FoM at Intel. Do to the higher yield rate the time to tape out is faster than 14nm.

They can model and post-silicon validate 7nm, in turn allowing them to do 10nm++ later.

Pretty much every single 7nm project is beyond the post-silicon validation phase when I did the first post. In regards, to all of this; 7nm is done and it is better than 14nm.

 

[dmens]

I am not. But, are you?
Intel has had NXE:3400B for sometime which in their words is enough for introduction[NPI Ramp]. They already have a plan to ramp with NXE:3400C which has higher uptimes. All the tools to get running with HVM will be at there places by 2H20/1Q21.

Are you actually equating spending capital to buy machinery and testers as indicative of process health? Could have argued the same about 10nm for the last half decade... oh wait.

They can model and post-silicon validate 7nm, in turn allowing them to do 10nm++ later.

Why would you model once you have silicon? You just run the silicon. Never mind, they don't have silicon.

Pretty much every single 7nm project is beyond the post-silicon validation phase when I did the first post. In regards, to all of this; 7nm is done and it is better than 14nm.

Beyond post silicon validation means the part is customer qualified and ready for general market production. So that is obviously wrong, no idea where you got that howler. Or anything else for that matter.

 

[NostaSeronx]

Beyond post silicon validation means the part is customer qualified and ready for general market production.

There is at least five A0 7nm products going around. Some of them might even be labeled as C0 stepping even though internally it is an A0 7nm part. The yields are that good.

 

[dmens]

There is at least five A0 7nm products going around. Some of them might even be labeled as C0 even though internally it is an A0 part.

Running A0 parts is the definition of being still in the process of silicon validation, so even if there are 7nm parts in labs (which still says absolutely nothing about process health), pretty much everything you posted is utter nonsense.

The yields are that good.

Why? Because there are parts in labs? Want to take a guess which year I first saw a Cannonlake in a lab?

 

[NostaSeronx]

Running A0 parts is the definition of being still in the process of silicon validation, so even if there are 7nm parts in labs (which still says absolutely nothing about process health), pretty much everything you posted is utter nonsense.

The month is July, the A0 was in Q1. August 2019 to the tour EUV corridors is the amount of time to get to post-silicon validation.

7nm is really really cooked.

 

[Exist50]

There is at least five A0 7nm products going around. Some of them might even be labeled as C0 stepping even though internally it is an A0 7nm part. The yields are that good.

Again, please take the trolling elsewhere.

 

[dmens]

August 2019 to the tour EUV corridors is the amount of time to get to post-silicon validation.

Are you on crack?

I saw the 36 core part before you did.

Yeah sure, and you also have a special pink Intel badge instead of the boring blue badge actual employees had to wear, which is why you saw parts that even CPU debug staffers have never heard of. It must swipe secret lab doors that my badge couldn't get in. LOL.

 

[NostaSeronx]

Yeah sure, and you also have a special pink Intel badge instead of the boring blue badge actual employees had to wear, which is why you saw parts that even CPU debug staffers have never heard of. It must swipe secret lab doors that my badge couldn't get in. LOL.

It was in public view for sometime.

Slot = 1 Cannonlake or 4 Tremont.
2x 6x6 = Big Core Phi
1x 6x3 = Big Atom Phi

Nothing about 10nm was concealed as it burned and products were canned.

I made a couple comments about 10nm back in the day. It only proves true, that Intel is leaky.

 

[dmens]

It was in public view for sometime.
View attachment 26355
Slot = 1 Cannonlake or 4 Tremont.
2x 6x6 = Big Core Phi
1x 6x3 = Big Atom Phi

So you didn't see the part, you saw it on a document which you totally misinterpreted? Cool. I'll just disregard everything you say from now on, good night.

 

[DrMrLordX]

Zen + to Zen 2 was 15 months. So Zen 3 can still see an october launch and still be on cadence.

If missing their roadmap completely for Zen4 is "on cadence" then hey, great. Not like Intel will be on time either. Comet Lake-S was 5 months late, Tiger Lake looks late. At this rate Alder Lake-S may be a 2022 CPU. Ignoring how late Intel really is when you consider the damage 10nm has done to their launch schedule.

Intel will be the last one laughing, when they eventually do roll out Alder Lake on 10nm+

Okay. Why?