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Intel 10nm and GF 7nm at IEDM 2017

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ksec

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Edit: Sorry for the double post.

Few more things to add.

1. I wonder if the new 4G Modem will be on 22FFL. Because it surely looks like very good fit for the purpose. And the timing makes sense as well.

2. It is finally looking like Intel is serious about Custom Fab. Not sure about tooling and ecosystem around it, but at least they have a product ( node ) that is attractive enough.

3. Turns out the rumours of trying to get Huawei wasn't without any merit.

4. I wonder why Intel decide to call it "22", when they could have name it something smaller for marketing purpose, after all Intel is very good at the name deceiving game in their consumer product, i wonder if it was some engineering pride in their Node naming scheme.

5. The end game of Intel according to a few sources were to get Apple to integrate their modem into their SoC using Intel's Fab. While that is unlikely to Apple because it is likely Apple are already designing their own Modem, at least the Fabbing side seems possible ( For now ).

6. We got Intel sticking AMD Graphics in their chip, how about Intel Fabbing for AMD Radeon Graphics. ( Hell really would frozen over )
 
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goldstone77

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Dec 12, 2017
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http://semimd.com/chipworks/

In 37.2 IBM/GLOBALFOUNDRIES studied the relative impacts of germanium content vs. strain on the performance of SiGe channels in strained SiGe p-FinFETs and planar devices on a strain-relaxed buffer (SRB) substrate. Last year GF/IBM/Samsung gave a paper on a SRB-based 7-nm process [2], and we looked at it in a follow-up blog.
This looks like further work to set some more parameters; the devices had different strain configurations, Ge channel compositions and surface properties. The inclusion of planar devices likely provides a baseline, but also may have useful data for the FDSOI processes at GF (no mention of FDSOI in the abstract). The fin shape is more rectangular than in last year’s paper – is the process evolving that way?

By comparing the transistor electrical properties of SiGe pFETs on SRB with those on Si substrate, the influence of strain and Ge content in the channel on device performance is decoupled from factors such as gate stack quality, reliability, and carrier transport.

The authors found that, independent of strain, increasing Ge content led to unstable gate stacks with greater interface trap charges and relatively low hole mobility, although it improves NBTI reliability. Carrier transport is predominantly controlled by the channel strain, and a (100) substrate crystal orientation helps optimize the effects of strain for both n- and p-FinFETs.

Process flows for SiGe planar pFETs and pFinFETs fabricated on SRB virtual and on Si substrates (source: IEDM/IBM/GF) TEM images of a Si fin after M1 metallization; STEM (left) HAADF (center) and (right) EDX. No Ge diffusion from the SRB to the Si active fin is observed (source: IEDM/IBM/GF)
37.3 is an invited IBM talk on gate-stack engineering for gate-first and RMG transistors, so again keeping consideration of FDSOI applications. Key process details are disclosed to achieve optimized devices with near-ideal SS, excellent NBTI, mobility and transconductance at scaled-EOTs. Aggressively-scaled fins with WFIN=6.4nm and excellent short-channel characteristics are also demonstrated.

imec/Applied Materials claim the first circuit built with Si nanowire transistors in 37.4 . They built functional ring oscillator test circuits using stacked Si NWFETs, with devices that featured in-situ doped source/drain structures and dual-work-function metal gates. A SiN STI liner was used to suppress fin deformation and improve shape control; a high-selectivity etch was used for nanowire/nanosheet release and inner spacer cavity formation, with no silicon reflow; and a new metallization process for n-type devices led to greater tunability of threshold voltage.

(a) NWFET structure after inner spacer fill and etchback; (b) after source/drain (S/D) epitaxy; (c) TEM view after S/D epitaxy (source: IEDM/imec/Appled Materials)
National Taiwan University also claims a first in 37.5, this time the first stacked GeSn pGAA-FETs. Good crystalline quality is achieved from CVD-grown stacked GeSn layers. Using Ge barriers as sacrificial layers and an ultrasonic-assisted hydrogen peroxide etching technique, the GeSn 60 nm channel has record high Ion of 1850 uA/um, with SS=88 mV/dec.
 

raghu78

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Aug 23, 2012
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Fantastic article by Scotten Jones of semiwiki. GF 7nm seems to have some key advantages.

https://www.semiwiki.com/forum/content/7191-iedm-2017-intel-versus-globalfoundries-leading-edge.html

1. GF 7nm SRAM is more dense. The advantage is 13% for high density and 20% for high performance.
High density SRAM cell size - GF 7nm 0.0269 sq um vs Intel 10nm 0.0312 sq um.
High performance SRAM cell size - GF 7nm 0.0353 sq um vs Intel 10nm 0.0441 sq um.

2. GF 7nm process seems to have more rectangular fins than the Intel process which should help in performance.

3. GF 7nm fin pitch is 30nm . Intel 10nm fin pitch is 34nm.

4. Transistor area is 8.5% lower for GF (30 x 56=1680) vs Intel (34 x 54=1836) . GF 7nm has a 8.5% lower cell size (56 x 40 x 6 = 13440 sq nm) vs Intel 10nm (54 x 36 x 7.56 = 14697 sq nm).

5. Scotten Jones calculated 103 mn tr per sq mm for Intel 10nm and 90.5 mn tr per sq mm for GF 7nm using Intel's logic density metric. Intel's contact over active gate is the reason for the logic density advantage.

Scotten is hearing that Intel 10nm is delayed to late 2018 or even 2019. GF 7nm is looking on track for risk production in H1 2018 and ramp to HVM in H1 2019.
 

Yotsugi

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Oct 16, 2017
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1. GF 7nm SRAM is more dense. The advantage is 13% for high density and 20% for high performance.
High density SRAM cell size - GF 7nm 0.0269 sq um vs Intel 10nm 0.0312 sq um.
High performance SRAM cell size - GF 7nm 0.0353 sq um vs Intel 10nm 0.0441 sq um.
20% advantage with HP cells?
7SoC is offering HP cells?
Ayy.
 

itsmydamnation

Platinum Member
Feb 6, 2011
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to me this is the key takeway:

3.0 Conclusion
Comparing Intel's 10nm process to GF's 7nm process they are more similar than they are different. Since both companies are solving the same difficult physics problems this is in some ways not surprising.
So largely speaking in late 18 and into 19 its all going to come down to uarch and SOC configuration.
 

Dayman1225

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Aug 14, 2017
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Edit: Sorry for the double post.

Few more things to add.

1. I wonder if the new 4G Modem will be on 22FFL. Because it surely looks like very good fit for the purpose. And the timing makes sense as well.

2. It is finally looking like Intel is serious about Custom Fab. Not sure about tooling and ecosystem around it, but at least they have a product ( node ) that is attractive enough.

3. Turns out the rumours of trying to get Huawei wasn't without any merit.

4. I wonder why Intel decide to call it "22", when they could have name it something smaller for marketing purpose, after all Intel is very good at the name deceiving game in their consumer product, i wonder if it was some engineering pride in their Node naming scheme.

5. The end game of Intel according to a few sources were to get Apple to integrate their modem into their SoC using Intel's Fab. While that is unlikely to Apple because it is likely Apple are already designing their own Modem, at least the Fabbing side seems possible ( For now ).

6. We got Intel sticking AMD Graphics in their chip, how about Intel Fabbing for AMD Radeon Graphics. ( Hell really would frozen over )
1. I believe the XMM7560 is based on 14nm, then the XMM7660 and XMM8060 based on 10nm

2. This is the supposed 22nm FFL ecosystem according to Intel

This slide is from September and from this PDF

3. The real question is, did Intel ever get anything from that...

4. Intel has been trying to get the Fab industry to move to a different way to measure density/size, so I assume its that(?) and if it turns out better than expected they kinda upsold their 22nm

5. It'll be interesting to see if that happens, I have had a few people tell me their may be merit to the rumor but its quite muddy and they are not sure

6. I don't think Intel want's to be in the business of enabling their competitors, nor do I think AMD want's Intel, their rival to be controlling yields and pricing, but hey you never know...
 

CatMerc

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Jul 16, 2016
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Here's an image I photoshopped to illustrate the process lead loss. I took an Intel marketing slide and injected into it up to date data.

7LP - GloFo
7FF - TSMC
7LPE - Samsung
 

goldstone77

Senior member
Dec 12, 2017
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Here's an image I photoshopped to illustrate the process lead loss. I took an Intel marketing slide and injected into it up to date data.

7LP - GloFo
7FF - TSMC
7LPE - Samsung
I like it! Also, I received your first "rough" draft to my email! I liked it as well!
 

goldstone77

Senior member
Dec 12, 2017
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Actually, that's not clear that Charlie is confirming what was said about 7nm, rather confirming what he said about 10nm.
Charlie has been saying there are significant issues with Intel's 10nm for over a year now, and it was more than just a couple things!
 

goldstone77

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Dec 12, 2017
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I've tried to do a closer side by side comparison, scaling is still off a little but not as much as the original.

I include information from Synopsys for clarity.


Edit:
We know that Intel's fin's are 46nm high. We do not know how tall GlobalFoundries fins are yet.


1.1 Intel 10nm
The key characteristics of the process are summarized as follows:
Fins - The fins are patterned with SAQP and have a 34nm pitch, are 7nm wide and 46nm high. This is Intel's third generation FinFET process. An interesting comment during the talk was that fin height can be optimized by product within an approximately 10nm range. The 46nm height quoted is slightly below the middle of the 10nm range.
1.2 GF 7nm
The key characteristics of the technology are:
Fins - The fins are patterned with SAQP and have a 30nm pitch. This is listed as GF's third generation FinFET process, GF's 14nm process was their first generation FinFETs, I am not sure what the second generation was, perhaps an enhanced 14nm version.
We know the pitch is 30nm, but we don't know width or height? This would be nice to know to see how close GF's height is to the 7nm L/W ~2.5 ratio.
 
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goldstone77

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Dec 12, 2017
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@goldstone77 Looks to be about 42-43nm for fin height:

Taking a screenshot and pasting it too MS Paint, and then blowing up the image to 400% I got the following calculation using rulers and gridlines.
I measured the width for each fin cut the number in half and added to 1 side to get the exact middle, which his centerline was off to the right a touch or 2. Then I measured first grey dot starting on top to the bottom of his red line. My question is the bottom of his line the accurate position?
269.5-411 = 30/141.5 = 0.212
654-454 = 200*0.212 = 42.4nm height



Using the same measuring methodology he used on GlobalFoundries for Intel gives me a much larger height than reported by Intel which is 46nm.
162-136 = 26/2 = 13 + 136 = 149 to give me my center line for left fin
286-261 = 25/2 = 12.5 + 261 = 273 to give me my center line for right fin
273 - 149 = 124 = 34 34/124 = 0.274
310 - 110 = 200*0.274 = 54.8nm Height close to the 53nm fin height reported on the image.

Edit: Intel's original picture was crooked and I tried to level it out the best I could to get a more accurate measurement.
2nd Edit: CNL will be 46nm height
 
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Dayman1225

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Taking a screenshot and pasting it too MS Paint, and then blowing up the image to 400% I got the following calculation using rulers and gridlines.
I measured the width for each fin cut the number in half and added to 1 side to get the exact middle, which his centerline was off to the right a touch or 2. Then I measured first grey dot starting on top to the bottom of his red line. My question is the bottom of his line the accurate position?
269.5-411 = 30/141.5 = 0.212
654-454 = 200*0.212 = 42.4nm height



Using the same measuring methodology he used on GlobalFoundries for Intel gives me a much larger height than reported by Intel which is 46nm.
162-136 = 26/2 = 13 + 136 = 149 to give me my center line for left fin
286-261 = 25/2 = 12.5 + 261 = 273 to give me my center line for right fin
273 - 149 = 124 = 34 34/124 = 0.274
310 - 110 = 54.8nm Height

Edit: Intel's original picture was crooked and I tried to level it out the best I could to get a more accurate measurement.
The image Intel released is of a 53nm fin height, which is not the height they use for CNL, they use 46nm for CNL.

 
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goldstone77

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This is starting to look like a really close shootout at 10nm and 7nm! Exciting! Now, let's see those price cuts across the board that we want!
 

Dayman1225

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Another article in the long list of articles published by semiaccurate on intel's 10nm issues. This has become a disaster for them.

https://semiaccurate.com/2017/12/20/state-intels-10nm-process/

What in the world has caused the train at intel to go so badly off the rails? And now the reports of not only 10nm problems but also CNL architectural problems as well.
If I had the subscription i'd be able to answer your questions, but from what I here 10nm process problems mostly boil down to Cobalt integration. CNL I have no idea about.
 

raghu78

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Aug 23, 2012
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So, it seems it's a fairly accurate measurement.
I think his measurement is off because he does not count from the top of the silicon substrate. Since the top of the substrate is not a flat plane I measured from the lowest point of the U shape in between the fins. I got 46nm fin height for GF. Anyway I looked at Intel 14nm transistor which has fin height 42nm and fin pitch 42nm and it looks like the way I measured is correct. You could do your own cross checking with Intel 14nm transistor.

http://www.legitreviews.com/intel-broadwell-architecture-preview-intel-core-m-and-broadwell-y_148500/2
 

goldstone77

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What is the state of Intel’s 10nm process?
Analysis: A long look at what was, is, and probably will be
Dec 20, 2017 by Charlie Demerjian
Intel seems to be trying to hide the state of it’s 10nm process from the financial community. SemiAccurate feels that if they knew what was really going on, it would lead to some very uncomfortable questions from analysts.

State of Play – 10nm and Fading:

From the time we exclusively told you about 10nm Cannon Lake’s return from the fab, it was clear something was off. To say yields were bad was understating things to a degree that even the classic British humorists would not dare to delve. Normally from tapeout to product on the shelves, Intel takes ~12 months for server SKUs, less for consumer. According to SemiAccurate moles, it has been ~16 months and counting.

Intel is insistent nothing is wrong but if you look at their recent Manufacturing Day messaging, one thing stood out. That thing is 20+ years of stating process progress was overturned with a new way of measuring progress that said that the 2+ year slip, at that time, for the 10nm process was not actually a problem, it was a technological breakthrough instead. SemiAccurate’s story above took so long to write after Manufacturing day because we had to stop laughing long enough for our eyes to come back into focus.


Ask yourself this, do companies have a 20+ year track record of technical measurements suddenly change things? Does it signal anything to you if they do so when things appear to be going horribly wrong, product delayed 2+ years and so on? Do you find comfort in this new technical measurement showing that instead of the hard data showing things well off the rails which is no longer disclosed for some reason, instead it shows a major technological leap forward? Even if if completely contradicts the basic foundation of the company’s financial basis, essentially that shrinks lower cost and add performance? See why we were laughing so hard?

Track Records Like Clockwork:

If you recall the first Intel 32nm parts, Arrandale (Westmere), were released in January of 2010. As per the Tick-Tock architecture plan there should have been a new architecture in January of 2011 and a shrink of that architecture in January of 2012. Sandy Bridge, the 32nm new architecture came out on time, as did the Ivy Bridge shrink. All is good so far.

Haswell was the new architecture on 22nm and, well, it wasn’t exactly on time, ~6 months late with a June 2013 release. We won’t get into the weeds discussing the long tails of older processes but the short version is that 22nm yields were still so low at this point that Intel was heavily pushing 32nm parts to OEMs and APAC countries to keep margins up. The normal swift cutover of sales from an old process to a new wasn’t publicly messaged this time around and Intel hasn’t talked about it since. For some reason SemiAccurate does not find this curious.

If you go to China and look at what the white box vendors sell, you will see they are still doing quite a brisk business in Haswell (22nm) CPUs, new ones. Not sure what this implies since it contradicts the official messaging about how Intel makes money, but feel free to do the research yourself. Officially those chips are vastly more expensive to make than the 14nm equivalents but they must be coming from somewhere, right? And who knows why Intel would do this in light of the official cost structure messaging.

The shrink to 14nm was heralded by Broadwell which officially came out in September of 2014, again an ~15 month release or another ~3 month delay. Intel claimed, correctly, that 14nm shipped for revenue in 2014 as promised. If you were cynical you would point out two things. First Intel shipped only the lowest volume, 2C GT1/2, lowest power parts in quantities that meant no one could realistically make products with them. Secondly you might consider that one SemiAccurate mole pointed out that Intel management pays bonuses based on when certain products and processes ship. 14nm shipped ‘on time’ by that metric, but we aren’t that cynical.

The usable 14nm parts shipped in January of 2015 or ~18 months after Broadwell actually came out. If you take the first September 2014 date, the shift from 22nm to 14nm took 2.25 years, 2.5 years if you take the real date into account. In any case it was a slip, Tick-Tock was a year off by this point and slipping. If you don’t think so, look at Skylake, the 14nm new architecture, it shipped in September of 2015 or ~9 months after Broadwell. Was it early or was it on time and Broadwell was late? Your call.

The Rails Are Over There:

Now if you look at Intel roadmaps of yore, the cadence should have gone 32nm (Westmere/Arrandale) in 2010, Sandy Bridge in 2011, Ivy Brige in 2012, Haswell in 2013, Broadwell in 2014, Sky Lake in 2015, Cannon Lake (10nm) in January 2016, Icelake (10nm) in January of 2017, and Tigerlake/Firelake (7nm) at CES in about 2 weeks aka January 2018. Instead there were the slips described above and Cannon, due ~2 years ago, isn’t out. Instead we have multiple “new architectures” that seem to pop up on the Intel roadmaps as soon as OEMs need to start production on the 10nm parts that were previously there.

The first of these was Kaby Lake which we exclusively told you popped up in May of 2015. It was a rename with a minor uncore change or two which is now a ‘new architecture’ and ‘new generation of Core’ in Intel parlance. 10nm Cannon was pushed out a year. When it came time for Cannon to ship after Kaby, yes you guessed it, Coffee Lake popped up on the roadmaps. Still 14nm.

That was a year ago and Cannon on 10nm was definitely going to ship in late 2017 or early 2018. Which meant, wait for it, when that time rolled around we get… 14nm Whiskey Lake, another ‘new architecture’ and ‘new generation of Core’! Be still my beating heart. Rumors about a 14nm part after Whiskey are making the rounds now too.

One aside to think about, Intel’s official claims versus reality. Officially these 14nm products are on 14+, 14++, and 14+++ processes which are, again officially, big steps forward. SemiAccurate went into great detail about why this wasn’t true earlier, these are just the standard mid-life PDK updates that bring minor benefits, mostly from a relayout of the chip, not the process. It was about this time that Intel changed policy and refused to give out transistor counts and die sizes, even on released products. Why? What do you think that data would show about Skylake, Kaby Lake, Coffee Lake, and soon Whiskey Lake? Do you think it would show massive area gains that the company claims the +/++/+++ processes bring?

All isn’t lost however, 10nm is now set for late 2018, officially, and that is where things really begin. Subscribers with weak hearts please stop reading here, if you think the 2+ year delay on 10nm is bad or believe Intel’s Hyperscaling distractions, this next bit won’t be of much comfort.

Note: The following is for professional and student level subscribers.

Disclosures: Charlie Demerjian and Stone Arch Networking Services, Inc. have no consulting relationships, investment relationships, or hold any investment positions with any of the companies mentioned in this report.
 

goldstone77

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I think his measurement is off because he does not count from the top of the silicon substrate. Since the top of the substrate is not a flat plane I measured from the lowest point of the U shape in between the fins. I got 46nm fin height for GF. Anyway I looked at Intel 14nm transistor which has fin height 42nm and fin pitch 42nm and it looks like the way I measured is correct. You could do your own cross checking with Intel 14nm transistor.

http://www.legitreviews.com/intel-broadwell-architecture-preview-intel-core-m-and-broadwell-y_148500/2
Looking at these images of measuring I have to say you are right that he didn't go down far enough, which is why I asked if it was the right way to measure it. The picture isn't visible enough to be sure you are getting an accurate measurement since you can't see the left of right sides to make the measurement. But all that being said I think he is in the ball park. Even if I measure below his reference point where I have a down facing pointer is measure 46.07nm even if we can't see the left and right sides accurately. Edit: 46.07nm is what I got for the exact same way you measured. 2nd Edit: look at my measurement for the Intel 10nm. His measurement would be closer to the right measurement using the same methodology. The fact I was so close the Intel measurement makes me believe it's closer the 42.4nm height I got earlier until I can get a more accurate point of reference it's in the ballpark.

 
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raghu78

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Looking at these images of measuring I have to say you are right that he didn't go down far enough, which is why I asked if it was the right way to measure it. The picture isn't visible enough to be sure you are getting an accurate measurement since you can't see the left of right sides to make the measurement. But all that being said I think he is in the ball park. Even if I measure below his reference point where I have a down facing pointer is measure 46.07nm even if we can't see the left and right sides accurately. Edit: 46.07nm is what I got for the exact same way you measured. 2nd Edit: look at my measurement for the Intel 10nm. His measurement would be closer to the right measurement using the same methodology. The fact I was so close the Intel measurement makes me believe it's closer the 42.4nm height I got earlier until I can get a more accurate point of reference it's in the ballpark.


I was able to verify my method of measuring is correct with Intel 14nm transistor which has 42nm fin pitch and 42nm fin height. Anyway as of now I think GF's 7nm has a 46nm fin height.
 

goldstone77

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Dec 12, 2017
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I was able to verify my method of measuring is correct with Intel 14nm transistor which has 42nm fin pitch and 42nm fin height. Anyway as of now I think GF's 7nm has a 46nm fin height.
Can you provide me a link to the measurements for that 14nm picture, so I can double check all 3 pictures.

Edit: I say this because for the 10nm I got 52.88nm whitch is really close to Intel's 53nm, which is why I think the 42.4nm height measurement is really close.
 

goldstone77

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I did calculations for samsung, and fin height ~42nm(42.81nm left; 42nm right) using the same methodology.
 

CHADBOGA

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This is starting to look like a really close shootout at 10nm and 7nm! Exciting! Now, let's see those price cuts across the board that we want!
Price cuts would be good, but I want to see improvements in single core performance, which I hope these new processes deliver in a significant way.
 

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