How high will ivy bridge overclock

[Idontcare]

So if I'm reading this correctly, compared to Sandy Bridge, Ivy Bridge will have less heat rate (Watts) but more heat flux (W/m^2) right? This would seem to indicate that good contact (lapping) and high thermal conductivity (Cu cooler or at least the CPU contact area) for optimal cooling/overclocking. And/or water to increase heat transfer.

Yep.

Water or good air (NH-D14), but all cooling solutions will be challenged more with IB than they would be with SB.

And think about the nearly straight shrinks. A node shrink typically reduces power-usage ~20% on a normalized basis (20% less heat for same xtor count, clockspeed, die design) but it reduces the diesize by ~40%.

Watts goes down but not as fast as mm^2, so W/mm^2 goes up.

This is everyone's challenge in the industry. If you just keep shrinking your chips then you reach a point where the node shrink enabled reduction in power-consumption alone is not enough to keep temperatures in check because the heat dissipation requirement is too high.

 

[SickBeast]

What's the thermal limit of these chips? I know of people with Intel chips that easily hit 80C.

 

[Puppies04]

What's the thermal limit of these chips? I know of people with Intel chips that easily hit 80C.

I was trying to find this out last night, had a little scout around google but couldn't find the TJmax.

 

[epidemis]

Why will there be less heat????

Because 20% less wattage is going trough the chip? (TDP was reduced 20%).

Reason:

Improved reduction of leaking because of the FinFET structure. Less power needed to bridge a small distance. If transistor power didn't scale we wouldn't see any improvements in performance metrics in semiconductors.

 

[bunnyfubbles]

still holding out hope for an amazing overclock, however I'm also kind of hoping all this speculation of Ivy not doing much better than Sandy turns out to be true as it would then make it really easy to just go all in with s2011 and a 3930K.

 

[Puppies04]

Because 20% less wattage is going trough the chip? (TDP was reduced 20%).

Reason:

Improved reduction of leaking because of the FinFET structure. Less power needed to bridge a small distance. If transistor power didn't scale we wouldn't see any improvements in performance metrics in semiconductors.

And as IDC pointed out the core area has reduced by 40% so 20% less heat in an area reduced by 40% = more heat per mm2 which is what we were talking about further up the page. Nobody cares if there is less total heat (within reason) all that matters is core temp (this is pretty much what I said in the rest of that post you just decided to take 1 sentence from to try and prove a point)

 

[Puppies04]

still holding out hope for an amazing overclock, however I'm also kind of hoping all this speculation of Ivy not doing much better than Sandy turns out to be true as it would then make it really easy to just go all in with s2011 and a 3930K.

Maybe they will be safer to clock to 5ghz with the correct cooling solution but as I still haven't heard of anyone running 5ghz on SB destroying their chip yet that will be a little hard to prove.

We still hear the same "don't go above 1.35-1.4v on SB or you risk your chip degrading. But while it seems these are safe numbers nobody has yet shown me proof that 1.45-1.5-1.55v are unsafe voltages especially with a decent watercooling setup which can keep temps down to "safe" levels.

 

[Phynaz]

Yep.

Water or good air (NH-D14), but all cooling solutions will be challenged more with IB than they would be with SB.

And think about the nearly straight shrinks. A node shrink typically reduces power-usage ~20% on a normalized basis (20% less heat for same xtor count, clockspeed, die design) but it reduces the diesize by ~40%.

Watts goes down but not as fast as mm^2, so W/mm^2 goes up.

This is everyone's challenge in the industry. If you just keep shrinking your chips then you reach a point where the node shrink enabled reduction in power-consumption alone is not enough to keep temperatures in check because the heat dissipation requirement is too high.

Back in the 65nm time-frame or there about, I remember an IBM scientist commenting on this. He wrote a blurb that if power density continued on the same path as it was then (remember this was when power consumption was going through the roof at the same time feature size was decreasing) that they could predict a time that CPU cores would generate the heat density of a nuclear reactor.

This paper from Intel claims that had they continued down the P4 path, they would have exceeded that already, and would be on the way to rocket nozzle levels of heat.
http://www.lems.brown.edu/~iris/dass11/Pant-DASS.pdf

 

[bunnyfubbles]

Maybe they will be safer to clock to 5ghz with the correct cooling solution but as I still haven't heard of anyone running 5ghz on SB destroying their chip yet that will be a little hard to prove.

We still hear the same "don't go above 1.35-1.4v on SB or you risk your chip degrading. But while it seems these are safe numbers nobody has yet shown me proof that 1.45-1.5-1.55v are unsafe voltages especially with a decent watercooling setup which can keep temps down to "safe" levels.

I'm not really worried about degrading my chip as I do upgrade about once a year on average

biggest problem really is 24/7 stability with tolerable levels of heat and noise output

If I'm going to have to upgrade to a decent water setup just for Ivy I might as well just go for SB-E which have been proving to be able to hit in the high 4s if not 5GHz with the newest batch of chips. Heck, I'm at the point where I could use the extra cores anyway, although I also need higher IPC and sheer clockrate in single/dual thread scenarios for apps that simply aren't that efficient with multiple threads. But if Ivy can't get much beyond 5.2 it simply won't be worth it for me.

 

[SHAQ]

I've had my 920 at 1.4v for 3 years now. Still at the same OC but it doesn't run at high loads very often and I turn it off at night.

 

[Puppies04]

I've had my 920 at 1.4v for 3 years now. Still at the same OC but it doesn't run at high loads very often and I turn it off at night.

I don't know if you are trying to infer that this has anything to do with SB or IB safe voltages but trust me it doesn't. Your chip is 45nm hence it should be able to take higher voltage without degrading, SB is 32nm and IB is 22nm a whole different ballpark from your CPU.

Edit. Also we have to keep in mind that IB has a completly new transistor design so we are pretty much back at square 1 (which we seem to be at anyway, as I stated before I am yet to see any feedback about what sort of voltages SB chips are breaking at)

 

[TidusZ]

I've had my 920 at 1.4v for 3 years now. Still at the same OC but it doesn't run at high loads very often and I turn it off at night.

My q9550 has been doing 4.25 at 1.392 v for over 3 years 24/7 no problem, but my e4300's 3.2 ghz overclock only lasted for 1 or 2 years and then I had to downclock quite a bit. I think I got pretty darn lucky with my q9550.

 

[podspi]

Back in the 65nm time-frame or there about, I remember an IBM scientist commenting on this. He wrote a blurb that if power density continued on the same path as it was then (remember this was when power consumption was going through the roof at the same time feature size was decreasing) that they could predict a time that CPU cores would generate the heat density of a nuclear reactor.

This paper from Intel claims that had they continued down the P4 path, they would have exceeded that already, and would be on the way to rocket nozzle levels of heat.
http://www.lems.brown.edu/~iris/dass11/Pant-DASS.pdf

It kind of makes you wonder what they were thinking... They must have known the architecture was a dead end...

 

[Phynaz]

I don't think so. I think everybody in the industry got caught off guard at 65nm.

Both IBM and Intel had leakage issues, AMD had binning (leakage?) issues. Everybody abandoned their high clocking projects at the same time. Only IBM is there now, with one product.

 

[Dadofamunky]

just saying

-wait till the real deal hits the benches

That pretty much covers it. We can't even guesstimate temps right now. And it's a completely new process with new transistor technology. We just don't know till it's officially released what the average ceiling will be.

I do know that if I do a chip swap, I will probably go water next time.

 

[Dufus]

What's the thermal limit of these chips? I know of people with Intel chips that easily hit 80C.

IIRC leaked results showed Tjmax at 105ºC which means if Tcase is similar to SNB then thermal resistance of core - IHS of IVB is quite a bit higher than SNB.

 

[SickBeast]

105C is very hot. Perhaps it will overclock well then. I don't mind if it runs hot; I think my HSF can handle it and it's quiet with the fans at full blast.

I really think these chips are going to bring on some new innovations in terms of cooling. I really think that watercooling especially should be able to generate less noise.

 

[PreferLinux]

Yep.

Water or good air (NH-D14), but all cooling solutions will be challenged more with IB than they would be with SB.

And think about the nearly straight shrinks. A node shrink typically reduces power-usage ~20% on a normalized basis (20% less heat for same xtor count, clockspeed, die design) but it reduces the diesize by ~40%.

Watts goes down but not as fast as mm^2, so W/mm^2 goes up.

This is everyone's challenge in the industry. If you just keep shrinking your chips then you reach a point where the node shrink enabled reduction in power-consumption alone is not enough to keep temperatures in check because the heat dissipation requirement is too high.

Why does the power usage only decrease roughly proportionally to the square root of the area (I think that is what it is doing)? I would have expected it to decrease linearly with area (halve the area, double the resistance and halve the capacitance, surely?).

 

[Idontcare]

Why does the power usage only decrease roughly proportionally to the square root of the area (I think that is what it is doing)? I would have expected it to decrease linearly with area (halve the area, double the resistance and halve the capacitance, surely?).

The ~20% rule of thumb is on a normalized basis, meaning same design, same clockspeed, but die-area and power (Vcc and static leakage) are scaled for the new node.

The power doesn't scale linearly with area mostly because the operating voltage doesn't down fast enough with each node shrink, and static leakage has generally increased (not decreases) with every node.

 

[PreferLinux]

The ~20% rule of thumb is on a normalized basis, meaning same design, same clockspeed, but die-area and power (Vcc and static leakage) are scaled for the new node.

The power doesn't scale linearly with area mostly because the operating voltage doesn't down fast enough with each node shrink, and static leakage has generally increased (not decreases) with every node.

OK, thanks.

 

[PreferLinux]

www.tweaktown.com/articles/4621/int...re_i7_3770k_and_core_i5_3570k_cpus/index.html
Interesting to see how the 3770K and 3570K temps compare – very different for a similar overclock.

 

[MisterMac]

www.tweaktown.com/articles/4621/intel_ivy_bridge_overclocking_with_the_core_i7_3770k_and_core_i5_3570k_cpus/index.html
Interesting to see how the 3770K and 3570K temps compare – very different for a similar overclock.

Is it just me, that sees VERY VERY low voltages, and seems like they just didn't push the ES samples very hard?

I can't seem to navigate they're wording saying:
"We simply couldn't get stable in 4,9 or 5,0! Sorry guys!"

They just stopped at X Overclock.

 

[psolord]

Is it just me, that sees VERY VERY low voltages, and seems like they just didn't push the ES samples very hard?

I can't seem to navigate they're wording saying:
"We simply couldn't get stable in 4,9 or 5,0! Sorry guys!"

They just stopped at X Overclock.

The low voltages are probably due to cpuz not reading them right. I've seen it before on a friend's 2500k. I was running 1.4V for 5Ghz and cpuz was showing something like 1.125V.

What really worries me, is the temperature of that infernal (literally) 3770k. God damn it why did I wait so long for this upgrade?

I hope there's something wrong with these ES chips, or I will seriously consider postponing again for Haswell or whatever.

 

[GrumpyMan]

The question I have is will it run cooler than the Ipad 3 when o/ced?

 

[Nemesis 1]

I'm not really worried about degrading my chip as I do upgrade about once a year on average

biggest problem really is 24/7 stability with tolerable levels of heat and noise output

If I'm going to have to upgrade to a decent water setup just for Ivy I might as well just go for SB-E which have been proving to be able to hit in the high 4s if not 5GHz with the newest batch of chips. Heck, I'm at the point where I could use the extra cores anyway, although I also need higher IPC and sheer clockrate in single/dual thread scenarios for apps that simply aren't that efficient with multiple threads. But if Ivy can't get much beyond 5.2 it simply won't be worth it for me.

These are all valid points . If the story of intel replacing 3770K 1 tme for free if you destroy it is true . I don't care what the debated safe voltage is . I will run mine @ 5.3ghz or 5.5 ghz or higher . I will not go above 1.45 v . If its true that intel will give us 1 replacement it just doesn't matter to myself . Others may have a differant thouughts on this . But as long as intel gives me a replacement no questions asked the Voltage question just doesn't matter on the first 3770k I purchase