Globalfoundries 7LP 7nm Leading Performance FINFET process and FX-7 ASIC platform

[Ajay]

Considering GloFo took over IBM's microelectronics business this could also be seen as a continuation of IBM's foundry tech.

The most important aspect to this arrangement is that GF picked up fab side personnel with well established relationships with IBM (as they were former IBMers). IBM kept their R&D personnel. Hopefully this works out well for GF. For the 14FF node GF had to go with Samsung's process, not IBM's.

 

[Mopetar]

Even having great process technology (a la IBM) is useless if you can't execute. There's a reason people refer to GF as Global Flounderies.

I'll be nothing short of amazed if they manage to meet their current time schedule. It would be great for AMD if they do as it would minimize process node differences between AMD and Intel more than they've been in recent memory, or perhaps ever. Imagine how much more of a monster Zen would be if it didn't hit a wall at 4 GHz. AMD could probably get away with no architecture improvements if the node shapes up to its potential.

 

[ajc9988]

Even having great process technology (a la IBM) is useless if you can't execute. There's a reason people refer to GF as Global Flounderies.

I'll be nothing short of amazed if they manage to meet their current time schedule. It would be great for AMD if they do as it would minimize process node differences between AMD and Intel more than they've been in recent memory, or perhaps ever. Imagine how much more of a monster Zen would be if it didn't hit a wall at 4 GHz. AMD could probably get away with no architecture improvements if the node shapes up to its potential.

What you have to remember is even GloFo has changed their approach. That acquisition turned them into the third largest fab, moving Intel to fourth. With the additional personnel, and considering the Samsung/IBM/GloFo research venture, which is to bring the new nodes to market, you have a much heavier hitting group to make the achievement of the timeline possible. Now, they have announced using IBM 7nm through licensing, and the IBM team was the group that was working on it before the acquisition. So, more than likely, we'll see a different result.

Meanwhile, all fabs are still waiting for EUV to hit commercial targets for implementation. At that point, everyone takes to the races.

 

[NTMBK]

What you have to remember is even GloFo has changed their approach. That acquisition turned them into the third largest fab, moving Intel to fourth. With the additional personnel, and considering the Samsung/IBM/GloFo research venture, which is to bring the new nodes to market, you have a much heavier hitting group to make the achievement of the timeline possible. Now, they have announced using IBM 7nm through licensing, and the IBM team was the group that was working on it before the acquisition. So, more than likely, we'll see a different result.

Meanwhile, all fabs are still waiting for EUV to hit commercial targets for implementation. At that point, everyone takes to the races.

GloFo has smashed together one failing fab business after another- IBM were failing so hard that they literally paid GloFo billions of dollars to take the fabs off their hands. I remain deeply skeptical.

 

[ajc9988]

GloFo has smashed together one failing fab business after another- IBM were failing so hard that they literally paid GloFo billions of dollars to take the fabs off their hands. I remain deeply skeptical.

GloFo has stayed afloat nevertheless. IBM was bleeding cash from the fab, but that is due to larger competitors. It is a very competitive business. They spun it off as AMD obviously did. Just because IBM's fab was not getting the business desired doesn't mean their processes were bad or that they didn't deliver. Now you have those two combined, you have the additional research agreement to bring the smaller nodes to mass production quicker. Having the number one and three largest fans working with the first company to achieve a 7nm and 5nm chip, and the all-around-gate to speed nodes and processes to market, which would take much longer otherwise, shouldn't be ignored.

Meanwhile, I point to Samsung and TSMC for timelines and nodes, which TSMC is already doing trappings for 7nm, Samsung is going to stay with 10nm longer, and GloFo already announced adopting IBM 7nm instead of licensing Samsung's (meaning Samsung has it, but isn't rushing as much). Intel, the fourth largest fab, has had problems with every node shrink since 14nm, which includes broadwell, which was a horrible chip, after having to put out devil's canyon because of the node not being ready and low yields. Now, 10nm is delayed AND we are seeing 3 process nodes per shrink. This is because they are having more trouble shrinking.

Other companies have had issues at 10nm also. It isn't unique to Intel. But, that is why GloFo focused on 7nm, as did TSMC which already have a 4GHz arm chip demo for HPC, which AMD is allowed to switch to if GloFo can't deliver. So, the arguments this is the same as historical events ignore intermediate developments, such as acquisition and research agreements.

 

[scannall]

GloFo has smashed together one failing fab business after another- IBM were failing so hard that they literally paid GloFo billions of dollars to take the fabs off their hands. I remain deeply skeptical.

IBM has always had a great process. But, they don't make the volume required to justify the expense of owning a fab. 5+ Ghz on a 12 core/48 thread CPU beast doesn't say "This process sucks".

 

[raghu78]

So we have official confirmation from Globalfoundries on GF 7LP specifications and comparison against TSMC N7, Intel 10nm and Samsung 7LPE by semiwiki.

https://www.semiwiki.com/forum/cont...alfoundries-discloses-7nm-process-detail.html

The data in the table illustrates the need for design-technology co-optimization (DTCO) at the leading edge. Intel and Samsung have the smallest CPP and MMP values but because GLOBALFOUNDRIES and TSMC offer 6T cells, they achieve smaller cell heights and ultimately GLOBALFOUNDRIES has the smallest CPP x Cell Height value. Samsung achieves the smallest SRAM cell size and through the use of EUV we expect Samsung to have the lowest mask count.

GF 7LP

MMP - 40nm
CPP - 56nm
HD SRAM cell size - 0.0269 sq mm

TSMC N7

MMP - 40nm
CPP - 57nm
HD SRAM cell size - 0.0270 sq mm

Intel 10nm

MMP - 36nm
CPP - 54nm
HD SRAM cell size - 0.0312 sq mm

Samsung 7LPE

MMP - 36nm
CPP - 54nm
HD SRAM cell size - 0.026 sq mm

 

[raghu78]

GF 7LP has the highest density due to the availability of 6T cells, followed closely by TSMC who also have 6T cells. Intel supports 7.56 track cells and Samsung supports 7.5 track cells .

Transistor density metric = Cell Height x Contacted Poly pitch
where Cell height = Minimum Metal Pitch x Track count.

Minimum Metal Pitch x Track count x Contacted Poly pitch

GF 7LP = 40 x 6 x 56 = 13440 sq nm
TSMC N7 = 40 x 6 x 57 = 13680
Samsung 7LPE = 36 x 7.5 x 54 = 14580
Intel 10nm = 36 x 7.56 x 54 = 14697

To give some perspective on how the last process generation from the above companies stacked up in terms of the above metric

https://www.semiwiki.com/forum/content/6713-14nm-16nm-10nm-7nm-what-we-know-now.html

Intel 14nm = 52 x 7.67 x 70 = 27919
Samsung / GF 14LPP = 64 x 7.5 x 78 = 37440
TSMC 16FF+ = 64 x 7.5 x 90 = 43200

For high performance GF 7LP will use 9T cells as will TSMC N7. I am not sure if Intel 10nm uses 9T cells for very high performance CPUs or 7.56T cells as advertised. For mobile designs GF 7LP and TSMC N7 offer the most dense process in the industry.

 

[Lodix]

//cloud.tapatalk.com/s/595d6f2f828b8/Samsung_Investor_Presentation_SLSI.pdf

In their latest financial investor Samaung LSI claim area reduction with 8nm and 6nm as the first shrink after EUV, maybe this numbers from Samsung are for their 8nm and they will use EUV for better perfomance/power and lower complexity with no area scalling at 7nmLPP. "Compdtitive in performance, power and scalling with EUV" and then they only market 6nm as just an area shrink of 7nm.

For a late 2019 target and using EUV would be a bit disappointing node size. TSMC will have 7mm+ with another ~20% shrink at 2019 too.

 

[raghu78]

Samsung's problem was betting on EUV for their 7nm node. They are now forced to scramble and come up with 8LPP to remain competitive in the short term till EUV is ready for volume production. The problem for Samsung is 8LPP is just not going to be able to compete with TSMC N7 or GF 7LP for area scaling, power and most importantly performance.

 

[ao_ika_red]

It's just the matter of how GloFo exploit 2018 timeline correctly. Because there's much less fabless company that attracted to advanced node ( if we compare it with 28nm era for example) due to skyrocketing cost, I think there's also less incentive to meet their schedule. But, as a customer I hope their optimistic schedule will come to fruition because there will be more excitement in CPU and GPU market in late 2018.

 

[ajc9988]

It's just the matter of how GloFo exploit 2018 timeline correctly. Because there's much less fabless company that attracted to advanced node ( if we compare it with 28nm era for example) due to skyrocketing cost, I think there's also less incentive to meet their schedule. But, as a customer I hope their optimistic schedule will come to fruition because there will be more excitement in CPU and GPU market in late 2018.

I disagree with that. It sounds like AMD will even work with them during risk production to meet it, taping out in Q4. The wafer supply agreement allows them to use alternative fabs if they cannot meet supply, which may include allowance for use of TSMC's 7nm. Considering this could effect Zen 2 delivery, I'd say there is plenty incentive to meet the deadline. That's before mentioning the IBM needs on that node. Those are large contracts with large implications. As such, I don't think it is as small a situation to miss the mark here.

Also, this node is using existing fab tech, not the new EUV which would compound the price, so utilizing DUV at both TSMC and GloFo means it will have price reductions without as large a jump in production costs as other node jumps.

It should be noted the quad patterning does increase costs, but was trying to keep it a bit general, both for discussion and for it not being my primary area of expertise.

 

[ao_ika_red]

I disagree with that. It sounds like AMD will even work with them during risk production to meet it, taping out in Q4. The wafer supply agreement allows them to use alternative fabs if they cannot meet supply, which may include allowance for use of TSMC's 7nm. Considering this could effect Zen 2 delivery, I'd say there is plenty incentive to meet the deadline. That's before mentioning the IBM needs on that node. Those are large contracts with large implications. As such, I don't think it is as small a situation to miss the mark here.

Also, this node is using existing fab tech, not the new EUV which would compound the price, so utilizing DUV at both TSMC and GloFo means it will have price reductions without as large a jump in production costs as other node jumps.

It should be noted the quad patterning does increase costs, but was trying to keep it a bit general, both for discussion and for it not being my primary area of expertise.

I think AMD's WSA clause is only activated if GloFo couldn't meet their schedule. The fact that their first risk production schedule is advanced up to 1H 2018 amazes me even more.
As far as I know, there's only 2 major companies that into GloFo 7nm campaign which are AMD (Zen 2) and IBM (Power 9). Unlike TSMC and Samsung whose already lock mobile and automotive contracts which I assume have much wider market penetration than AMD and IBM alone.

 

[Lodix]

Samsung's problem was betting on EUV for their 7nm node. They are now forced to scramble and come up with 8LPP to remain competitive in the short term till EUV is ready for volume production. The problem for Samsung is 8LPP is just not going to be able to compete with TSMC N7 or GF 7LP for area scaling, power and most importantly performance.

We agree. Samsung had to change plans to remain competitive but still that doesn't change my point. They claim an area reduction with 8nmLPP which will be ready some quarters later than TSMC 7nm and by the same time as GF's 7nm some time in 2H 2018. While their 7nm which uses EUV is targeted for 2019 and Samsung says it is mostly an improvement in power and performance while the next shrink will be 6nmLPP. So it is logical to guess that the numbers of their "7nm" that you quoted are for their 8nmLPP ( or close to ).

Also they give info about their 14nmLPU which is probably the same "14nm+" AMD will uses from GF for the next Zen revision. It is supposed to bring 15% better perfomance.

 

[ao_ika_red]

Also they give info about their 14nmLPU which is probably the same "14nm+" AMD will uses from GF for the next Zen revision. It is supposed to bring 15% better perfomance.

Help me verify this.
RX4xx chips were using samsung 14LPE
Zen and RX5xx chips are using samsung 14LPP
Zen+ and future RX will use samsung 14LPU
Are they correct?

 

[Lodix]

Help me verify this.
RX4xx chips were using samsung 14LPE
Zen and RX5xx chips are using samsung 14LPP
Zen+ and future RX will use samsung 14LPU
Are they correct?

All products from AMD at 14nm are using 14nmLPP or LPC.

 

[raghu78]

Help me verify this.
RX4xx chips were using samsung 14LPE
Zen and RX5xx chips are using samsung 14LPP
Zen+ and future RX will use samsung 14LPU
Are they correct?

I think Rx 4xx chips use 14 LPP , Rx 5xx use 14 LPC (same perf as 14 LPP but lower cost) and AMD 2018 products use 14nm+ . My guess is Pinnacle Ridge in Q1 2018, Raven Ridge in late Q4 2017, Vega 11 in Q1 2018 and a probable Vega 10 refresh in mid 2018 are all using 14nm+ . 14nm+ is most probably similar to 14LPU (15% better perf than 14 LPP).

 

[plopke]

Silly question : is there anything that could stop Intel from buying Global Foundries except market regulators? Just purely out of daydreaming curiosity 😛 , may be a bit too much off topic .

 

[ao_ika_red]

I think Rx 4xx chips use 14 LPP , Rx 5xx use 14 LPC (same perf as 14 LPP but lower cost) and AMD 2018 products use 14nm+ . My guess is Pinnacle Ridge in Q1 2018, Raven Ridge in late Q4 2017, Vega 11 in Q1 2018 and a probable Vega 10 refresh in mid 2018 are all using 14nm+ . 14nm+ is most probably similar to 14LPU (15% better perf than 14 LPP).

Well, that really explain why RX5xx chips do not have significant gain if we compare with RX4xx chips. Here's hoping 14nm+ will be translated into 14LPU. Samsung promises good gain for hi-perf chips using that node.

 

[scannall]

Silly question : is there anything that could stop Intel from buying Global Foundries except market regulators? Just purely out of daydreaming curiosity 😛 , may be a bit too much off topic .

Intel's shareholders. Process R&D and foundries are already a huge expense for them. Making that worse wouldn't help them in anyway at all.

 

[turtile]

Silly question : is there anything that could stop Intel from buying Global Foundries except market regulators? Just purely out of daydreaming curiosity 😛 , may be a bit too much off topic .

Well, they don't have enough cash to buy GF so they would have to use stock which likely won't get approved. It would make no sense to buy more fabs when they are trying to fill their own. They can easily open their fabs to others without buying out another foundry.

 

[ajc9988]

I think AMD's WSA clause is only activated if GloFo couldn't meet their schedule. The fact that their first risk production schedule is advanced up to 1H 2018 amazes me even more.
As far as I know, there's only 2 major companies that into GloFo 7nm campaign which are AMD (Zen 2) and IBM (Power 9). Unlike TSMC and Samsung whose already lock mobile and automotive contracts which I assume have much wider market penetration than AMD and IBM alone.

They have another provision that if they don't meet having enough wafers for production, it can switch also, but generally, yes, they have to miss schedule for the out.

And that is my larger point, if your two largest contracts can go if you can't deliver, you have extra incentive to meet the timeline.

I'm also looking at the normal 9-12 months on tape out to production volume and Su hinting at 7nm in Q3 2018, with volume most likely being Q4 or Q1 2019. They have hinted at, but not confirmed, Zen 3 by late 2019 and into 2020.

But it is the WSA that I see as providing the push, along with tape out.

 

[CatMerc]

Anandtech confirmed that RX 500 series is using 14nm LPP, not LPC.

 

[moinmoin]

And that is my larger point, if your two largest contracts can go if you can't deliver, you have extra incentive to meet the timeline.

I'm also looking at the normal 9-12 months on tape out to production volume and Su hinting at 7nm in Q3 2018, with volume most likely being Q4 or Q1 2019. They have hinted at, but not confirmed, Zen 3 by late 2019 and into 2020.

GloFo has the incentive, and AMD has the design (with the built in redundancy that we talked about before) that will result in usable chips even on low yield from the fab. So even in the worst case I'd expect availability of 7nm chips in some high margin markets before 7nm is ready for mass market volume.

 

[NostaSeronx]

GlobalFoundries has only access to 14LPe and 14LPP. The Globalfoundries 14nm+ node is HPP. Not to be confused as a better version of 14HP, which is SOI FinFETs. 14HPP which is Bulk FinFETs and is basically 14LPP with 7LP-styled transistors, MOL, etc, and such has higher performance.