- Apr 1, 2015
That is using the reasoning Intel gave for years, although Intel needed it because you wanted the process refined BEFORE trying the big die chips. Here, all chips are the same size and Epyc even goes down to 8 cores, which is 1 core per CCX. Mainstream cannot do that. Mobile cannot do that. The server chips can.I'm not really sure about EPYC and TR will get first treatment of 7nm. Because, as usual, a new process means low yield and AMD can't afford such loss. I bet they will use the smaller chip, either small GPU like P11 successor or mainstream version of Zen2.
After all, AMD hold their schedule very close to their chest, even I won't dare to bet when first mobile Raven Ridge will be delivered, let alone which process (LPP or 14+) they will be used.
Keep all your heads down, guys. It's just about prediction and speculation after all.
Now, as we have discussed above, 14nm+ may be the 7nm transistor style on 14nm. This would be doing similar to what is done by Intel, like Sandy for Ivy, Haswell for BW, and Coffee for cannon. So, since they can use as low as one working core per CCX, you could fill out the entire Epyc and TR lineups even with lower yields. You then use IF like they are now. Do you see why server side makes the most sense now?
Edit: also, the server line clocks lower than the mainstream and TR lines. This means if you have an imperfect die that qualifies, but at a lower speed, you don't have to eat the cost like the other lines you mentioned. Intel went with mobile because it has lower clocks for dual and quad cores.