Discussion AMD's Soundwave ARM APU: The Beginning of Transformation !!!

[soresu]

As long X86 is strategic, it won't die.

As long as legacy software exists x86 won't die.

Emulation might be fine for some, but for critical use cases of businesses and infrastructure reliant on legacy x86 code they are not going to risk "mostly fine" implementations ever.

 

[soresu]

2-3 Neoverse licensing hikes and they'll be crawling back and begging for mercy.

The thing is that Amazon and others like them with custom Neoverse based SoCs are not selling chips, they are selling VM instances.

Which means tracking exactly how many chips have been manufactured without ARM Ltd somehow having spies within TSMC or other foundries is going to be very difficult.

If ARM Ltd start pulling a fast one the licensees can just start playing creative accounting with how many chips they have actually ordered from foundries.

Or they can start modifying older Neoverse cores on the sly so that they are getting more performance for the same license cost.

 

[Thibsie]

Oh dear - at this rate Samsung and Mediatek will be the only big volume players using ARM Ltd's Cortex X CPU IP in consumer hw 😅

Which would like a giant fail to me. ARM ridiculed again.

 

[soresu]

Which would like a giant fail to me. ARM ridiculed again.

Not ridiculed per se.

Their cores seem to be quite competitive in the high and mid range, it's only the so called "efficiency" low range A5xx that has become worthy of ridicule for its relative inefficiency with the long time frame after A55 only to be replaced with A510 which didn't blowing anyone away and then A520 which seems pretty meh for a 2 yr update when compared to the gains of both A7xx and X9nn/Xn.

I'll eat my hat double time if A530 comes out with a sOoO style core and doubled perf/watt at ISO node, but I don't see that happening.

As far why other companies are going custom it's more a matter of product differentiation and was bound to happen (plus of course the companies licensing Neoverse V and N cores are basically subsidizing A7xx and X9nn development anyway so there's no need to worry on that score).

The question is if any new companies like Cix are going to step up and buy into the higher end ARM core consumer space with the broadening horizon of WoA opening up.

 

[soresu]

Where did the name Prometheus come from?

The only time I heard it mentioned outside of a Zen C core variant was MLID talking about it being the codename for Zen7 a yr ago.

 

[DZero]

Not ridiculed per se.

Their cores seem to be quite competitive in the high and mid range, it's only the so called "efficiency" low range A5xx that has become worthy of ridicule for its relative inefficiency with the long time frame after A55 only to be replaced with A510 which didn't blowing anyone away and then A520 which seems pretty meh for a 2 yr update when compared to the gains of both A7xx and X9nn/Xn.

I'll eat my hat double time if A530 comes out with a sOoO style core and doubled perf/watt at ISO node, but I don't see that happening.

As far why other companies are going custom it's more a matter of product differentiation and was bound to happen (plus of course the companies licensing Neoverse V and N cores are basically subsidizing A7xx and X9nn development anyway so there's no need to worry on that score).

The question is if any new companies like Cix are going to step up and buy into the higher end ARM core consumer space with the broadening horizon of WoA opening up.

In order cores are no longer useful in the phone and PC aspect, only works in the small things which don't need an interface, and even that is starting to lose the protagonism

 

[adroc_thurston]

The thing is that Amazon and others like them with custom Neoverse based SoCs are not selling chips, they are selling VM instances.

Which means tracking exactly how many chips have been manufactured without ARM Ltd somehow having spies within TSMC or other foundries is going to be very difficult.

Neoverse fees are per core shipped.
ARM doesn't have to track anything, it's in the licensing agreement.

 

[soresu]

Neoverse fees are per core shipped.
ARM doesn't have to track anything, it's in the licensing agreement.

So who tells them how many cores/chips then?

It has to be TSMC or the company that designed the SoC.

 

[soresu]

In order cores are no longer useful in the phone and PC aspect, only works in the small things which don't need an interface, and even that is starting to lose the protagonism

There is a mid point that seems to be developing in the research space between InO and OoO, thought I'm not sure if anyone has actually produced a CPU core based on these concepts as yet.

Some of them are on the level of 10s of milliwatts over the consumption of an in order core, but performing somewhere on the level of 70-95% of an out of order core of equal width.

 

[gdansk]

So who tells them how many cores/chips then?

It has to be TSMC or the company that designed the SoC.

Lying about core shipments is not a winning move or a cost-cutting measure. You will end up paying more damages and for lawyers the moment ARM notices revenue not growing despite more customers using Grav.

 

[soresu]

Lying about core shipments is not a winning move or a cost-cutting measure

I don't think so either, but within Amazon's VM instance business model of internal chip use as opposed to actually selling the chips on as Intel, AMD or Samsung do it seems like getting an accurate accounting of exact numbers would be difficult at best if they decided to fudge the numbers.

 

[adroc_thurston]

So who tells them how many cores/chips then

Amazon. They pay a flat fee per core shipped.

 

[StefanR5R]

There is a mid point that seems to be developing in the research space between InO and OoO, thought I'm not sure if anyone has actually produced a CPU core based on these concepts as yet.

Ah yes, this goes way back to this patent on cores which are neither in-order nor out-of-order, yet become simultaneously in-order and out-of-order if nobody is looking. AFAIU, it hasn't been productized yet, but nevertheless the inventor already made boatloads of money off it.

 

[soresu]

Ah yes, this goes way back to this patent on cores which are neither in-order nor out-of-order, yet become simultaneously in-order and out-of-order if nobody is looking. AFAIU, it hasn't been productized yet, but nevertheless the inventor already made boatloads of money off it.

Boatloads of money?

Sounds like big bois already came knocking and product is on roadmaps.

Either way there are many research papers on these "slice out of order" cores, so I imagine there are more than a handful of different patent holders in this new IP sector.

 

[soresu]

@StefanR5R here's the latest I could find, their claims are pretty impressive however barebones their implementation is likely to be...

Page 2 - Discussion - General CPU µArch Research Thread

Page 2 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

 

[MS_AT]

the inventor already made boatloads of money off it.

Any sources for that, an no, I don't mean the picture?😉

their claims are pretty impressive

Claims in scientific papers have to be impressive😉 And don't even dare to say you investigated something and it did not work out... Nobody would be interested in publishing...

 

[StefanR5R]

Any sources for that,

Spoiler

The notion that there is supposed to be something *between* "in order" and "out of order" reminded me of phenomena in quantum physics, in which something can be in two antagonistic states at once — until observed, at which point it collapses into either one or the other. Then, thinking of one W. Heisenberg reminded me of the other W. Heisenberg…


IGMC.

 

[Sgraffite]

Maybe Cyrix will come back making ARM CPUs

 

[Tigerick]

1. Power Efficiency

On the x86 side, the higher performance / higher frequency devices are the established market that our devices have to compete in, so that's where our design focus is. We could build the same Zen microarchitecture with an ARM ISA on top instead. We could deliver the same performance per watt. We don't view the ISA as a fundamental input to the design as far as power or performance.

Mike Clark mentioned above statement regarding performance per watt. For comparison, I have created a table comparing x86 and ARM with GeekBench 6 ST performance, and I hope nobody believe what Mike claimed about PPW. Qualcomm, Mediatek not to mention Apple's M4 are all surpassing AMD's KRK/STX in single thread performance with fanless design. You could argue Qualcomm's X Elite is performed slower than KRK/STX, but that is about to change with upcoming 18-core Oryon V3 by the end of this year.

AMD upcoming Venice server SoC which is fabbed by TSMC's N2 process is having 32C/64T per compute tile. We don't know what total TDP with 256-core but judging by the changing of the socket supporting 16-channel DDR5, Venice with 256/192 cores should require at least 600W power. Meanwhile, NV has pre-annouced custom ARM core, Vera/Olympus with 88-core supporting SMT but consumes just 50W. That's mean with 2 tiles link together through NVLink, NV could have Vera Superchip with 176c/352T consuming 100W only...Go figure

 

[Tigerick]

2. Performance

Architecture	Date Announced	Features	ARM core	Custom Core	RISC-V
ARMv8.6-A	Q4-2019	GEMM	Apple A17 Pro (N3B, Q3-2023)
ARMv8.7-A	Q4-2020	Oryon V1
ARMv9.0-A	Q1-2021 ?	SVE2 TME CCA	Cortex-X2 (2021) Cortex-X3 (N4, 2022)	Apple M3 (N3B, Q4-2023)	RVA-23 - SiFive P870
ARMv9.2-A	Q4-2020	SME	Cortex-X4 (N4P, 2023) Cortex-X925 (N3E, 2024)	Apple M4 (N3E, Q2-2024) Apple A18 Pro (N3E, Q3-2024)
ARMv9.3-A	Q4-2021	Non-maskable interrupts Instructions to optimize memcpy() and memset() style operations Enhancements to PAC Hinted conditional branches	C1 (N3P, Q3-2025)	Apple A19 Pro (N3P, Q3-2025) ?
ARMv9.4-A	Q4-2022	Virtual Memory System Architecture (VMSA) enhancements. SME2 Guarded Control Stack (GCS) Confidential Computing	C2 (N2, Q3-2026) ?	NV Vera ?
ARMv9.5-A	Q4-2023	FP8 support (E5M2 and E4M3 formats) added to SME2, SVE2, Advanced SIMD (Neon)	C3 (N2P, Q3-2027) ?
ARMv9.6-A	Q4-2024	Improved SME efficiency with structured sparsity and quarter tile operation New SVE instructions for expand/compact and finding first/last active element
ARMv9.7-A	Q4-2025	Targeted memory invalidation broadcasts Flexible resource management (MPAMv2) 6-bit data types for Artificial Intelligence Video-codecs updates GICv5
ARMv9.8-A	Q4-2026

Table said thousands of words...I also listed Risc-V latest profile, RVA23, the performance is about Cortex-X2 level. RISC-V still very behind in the development cycle, let's see how much improvement in newer profile..

 

[Tigerick]

3. The Arrival of LPDDR6

LPDDR6 will bring huge bump in memory bandwidth, that's mean all vendors will bump the core counts of CPU, GPU and NPU. With more cores, so does the power consumption. x86 with high clock speed won't be able to scale without big bump in power usage. There was rumor about Qualcomm's next gen X-Elite with 192-bit memory bus comes with 18 cores. And if my speculation is correct, upcoming Apple M5 Pro with 192-bit LPDDR6 should get bump of 14-core to 18-core as well ? We are talking about monolithics SoC, not chiplet design which is more expensive and power hungry..

	Grace	Vera	Vera Superchip		Turin / Dense	Venice SP8	Venice SP7	AMD Future ARM		Clearwater Forest
CPU	Neoverse V2	Olympus	Olympus		Zen 5 / 5c	Zen 6 / 6c	Zen 6c	Custom Armv9.4 w/SMT ?		CWF-SP
Boost Clock					4.1 GHz / 3.7 GHz
All-core	3.0 GHz				4.1 GHz / 3.35 GHz
L3 Cache	114 MB				32MB / 32MB per CCD	48MB / 128MB per CCD	128MB per CCD
Total L3 Cache	114 MB				512MB / 384MB	384MB / 512MB	768MB / 1024 MB			576 MB
CPU Tiles	1	1	2		16 / 12 + 1 IOD	8 / 4 + 1 IOD	6 / 8 + 2 IOD			4 x 3 + 2 IOD
Total Cores	72	88	176		128 / 192	96 / 128	192 / 256			288
Total Threads	72	176	352		256 / 384	192 / 256	384 / 512			288
TDP (CPU only)		50 W ?	100 W ?		500 W	350 - 400W ?	600 W ?
Memory	512-bit LPDDR5X	384-bit LPDDR6 ?	768-bit LPDDR6 ?		12-channel DDR5	8-channel DDR5-8000	16-channel DDR5-8000			12-channel DDR5-8000
Memory Bandwidth	240GB - 512 GB/s 480GB - 384 GB/s	614 GB/s	1228 GB/s		614 GB/s	512 GB/s	1 TB/s			650 GB/s

 

[Tigerick]

4. BOM

NV's upcoming N1X SoC should be entry ARM SoC targeting below $600 fanless tablet/notebook PC. 2+2 A725 might not be performance leader: they are in range of Mendocino/N200 with fanless design meanwhile AMD and Intel have to rely on the fans to keep up the performance.

 

[adroc_thurston]

NV's upcoming N1X SoC should be entry ARM SoC targeting below $600 fanless tablet/notebook PC.

Chefe N1x is the -halo comp, with 256b LPDDR5X and stuff.

 

[Tigerick]

5. WoA 12 / Windows Server for ARM

Have you wonder how Microsoft going to support upcoming ARM vendors like NV, AMD, Mediatek and Samsung? Microsoft could hard patch the OS to allow all upcoming CPU vendors to access low level kernel; Or Microsoft could launch brand new OS like Windows 12 ARM supporting all CPU vendors ?

According to Wiki, MacOS 15 has been updated to support ARMv9 in the operating system level. Microsoft could follow steps to modermize OS by supporting ARMv9 as well. That's mean Microsoft could launch Windows 12 by the end of this year with NV/AMD's Soundwave/Mediatek.

As for Windows Server ARM, it should be based on WoA12. The only issue is we don't have CPU vendors with flagship performance: if Microsoft is waiting for NV's Vera / AMD's Prometheus, then Microsoft could launch Windows Server on ARM by end of 2026...we shall see...

 

[Tigerick]

6. Soundwave - The Beginning of Transformation!

As I predicted many months ago, AMD's Soundwave SoC signals the beginning of transformation from x86 to ARM platform. Soundwave is not custom SoC for Microsoft, period. Saying AMD is making custom SoC for Microsoft does not understand how business works. AMD won't spend billions of dollars making SoC for Microsoft alone, AMD will have to create flagship SoC to compete with Qualcomm, NV and Mediatek for ARM PC market share.

Microsoft just launched latest Surface Pro 12 and Surface Laptop with Qualcomm's X Plus 8-core SoC. It is mainstream SoC targeting sub-$1000 PC market. We should assume Microsoft won't replace this model soon, then what family Microsoft will fit in with NV and AMD's SoC?

NV is rumored to launch three ARM SoC; I suspect the low-end model, N1X which might be manufactured by Intel's 3 process will be the choice for Surface Go family.

That left AMD's Soundwave which should/could be replacing X Elite model. X Elite is the flagship ARM SoC with 12-core CPU and 3.8TF GPU, then what should we expect for AMD's Soundwave? That's why I don't believe in MLID leaks about Soundwave specification.

What I believe:

• TSMC's N3P process targeting 2026 launch
• 16MB of MALL Cache

What I don't believe:

• 128-bit LPDDR5X-9600 - 96-bit LPDDR6 ?
• 2P + 4E total 6 cores. I am expecting 12-18 CPU cores
• 4 RDNA3.5 CU. I am expecting 16-24 CU
• NOT for 5-10W TDP
• External 5G Modem ?