You are really misinformed here.
Do you know how IPC is increased?
Do you know the process of increasing IPC increases structure SIZE and POWER?
Do you really think +40% comes free?
Do you realize how adding so many transistors in a smaller area with higher work done per cycle creates huge thermal density problems?
And how they affect the chip?
ALL of these factors are interlinked.
Forget process for now (capacitance, Vth and wire delay).
You either aim for a high IPC/low clocks design or a low IPC/high clock design.
More work per logic COSTS size/power!
There is no such thing as both possible in science!
Even when you have an excellent balance, it is about the process, the yields, and the market. Process factors are so tricky, many do not have a known cause with errors. Just 'poor reliability'.
I questioned you about Vth, capacitance and the rest of GloFo PROCESS qualities as soon as you were 'developing' them, and they still remain unanswered to date.
Show me ONE x86 desktop/server MFG that released a new uarch with MUCH higher IPC + higher core count + higher clocks + much lower power from their previous chip, in the past 15 years.
Just one.
OMG.
You make all the worldd best, most intellectual researchers seem so backwards
More stages->less logic per stage=deeper pipeline=higher latencies=lower IPC=higher possible clocks
Have a read of some FO4/IPC basics because you're reasoning is non-sensical and scientifically impossible:
http://www.cs.utexas.edu/users/skeckler/pubs/isca00.pdf
Table 7 shows you exactly what I've described.
Intel has a far superior process for all intents and purposes. Why did they not see superstellar gains?
Show me where they doubled cores, increased clocks, doubled caches and structures (added much higher IPC) AND decreased power at the top of their line.
AMD never clarified anything about WHICH Core at WHAT MHz/Voltage during WHICH workload under WHAT conditions for WHICH part of the traditional curve has the same energy per cycle.
In other words, it can really be used for nothing.
Sent from HTC 10
(Opinions are own)
I surrend. You are right. Zen will clock at 2GHz with P4 IPC and 220W TDP...
I wrote many things, based on known data on process, FO4 and other related stuff. You throw away all only by saying "no one ever did that so AMD can't" (obviously no one is INTEL), without explaining why.
Tell me how come A12 9800 clock at 4.0/4.2 with 65W including GPU on the shitty 28nm BULK process with HDL libraries without melting down.
Tell me how come it overclock at 4.9GHz on air on this shitty process without melting down.
Tell me how a 19 stage integer pipeline processor of the same company can have an higher FO4 than a 15-20 stage processor, when they passed from a 4 way scheduler to 6 1 way scheduler, that is FASTER. They are crazy? Why simplify the scheduler if this costs IPC? It's to clock higher.
Tell me how come a speed daemon design on a better process should clock lower. Because has high IPC? Because high IPC means higher consumption? This is true at same process. But Zen it's on 2 nodes better and finfet vs bulk. AMD stated SAME ENERGY/CYCLE per core between XV and Zen. This means that 2 Zen cores draw THE VERY SAME POWER an XV module at same frequency. So a 4 Zen core at 4GHz draw same power that the cores of an A12 9800, a 65W part INCLUDING the GPU. A 4Ghz base 8c Zen at 95W should be feasible.
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