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AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

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bjt2

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If that would be the case why are all rumors pointing to an All core base clock of 3.2 or 3.3ghz + yes I know TDP is 95w, but for the sake of performance and kicking Intel's but one could release the a black edition wit 4.0ghz all core base clock - since there are no hints pointing that way I doubt Zen will OC higher than 3.5-3.6ghz regardless how high the TDP will be.
The rumors are based on the last known ESs...
Bulldozer ESs were from 2.2 to 2.8GHz and the first batch started at 3.6 GHz base.
We are in similar situation.

I would expect low distance between ES and retail clocks on a known architecture (a tweak) on a known process...

But here we are with a new architecture on a new process and an A0 ES (a very first ES) has 3GHz of clock, with lower than BW-E consumption... This is not less than awesome, you bet.

Why on earth these clocks should be final?
 

Abwx

Diamond Member
Apr 2, 2011
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I didn't remember and didn't want to say something exaggerated, but nice to know... Even better...
So the odds to have 4GHz base and 4.8-5.0GHz turbo are increasing...
I didn't remember and didn't want to say something exaggerated, but nice to know... Even better...
So the odds to have 4GHz base and 4.8-5.0GHz turbo are increasing...
Relative speed betwwen the two processes = Transconductance/Capacitance, but in practice it s not as simple as that, the device is limited by the die local temperatures, wich si function of local densities of transistors that are switched at max fequency, like in the CPU pipeline, so despite better characteristics dont expect frequencies higher than what they have with Bristol Ridge.
 

guskline

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Apr 17, 2006
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According to some reviews, it reaches 4.8GHz on air on stock cooler, but this guy managed to have 4.9GHz: http://valid.x86.fr/6cpmvb
I suppose also with stock cooler.
That is a 65W Bistol Ridge apu showing 4 cpu cores and 8 gpu cores.

As I under stand it ZEN, and in particular the Summit ridge is, at top end consumer, a cpu only with 8 cores and 16 threads.
 
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bjt2

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Sep 11, 2016
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Relative speed betwwen the two processes = Transconductance/Capacitance, but in practice it s not as simple as that, the device is limited by the die local temperatures, wich si function of local densities of transistors that are switched at max fequency, like in the CPU pipeline, so despite better characteristics dont expect frequencies higher than what they have with Bristol Ridge.
I know that with double the transistor density, heat can become a problem, but the gains are so high that we should have an increase anyway... +50% transconductance, -20% capacitance, -83% leakage, less Vth... At same frequency the power can be half per transistor... And official AMD statements of same energy cycle per core says just that, because a Zen core has about the transistors of an XV module, or 2 XV cores. So two zen cores draw same power of 2 XV cores, or an XV module. But 2 zen cores have about the same transistors of 2 XV modules or 4XV cores. So the 14nm power consumption, per transistor, is about half...
This means that a 4 core Zen at 4GHz draws like 4 XV cores at 4GHz, or less than 65W (A12 9800 is an APU).
Stripping off the GPU and doubling the cores, I think that in 95W a 4GHz base Zen is feasible, with a turbo more than 4.3GHz (like the 95W bristolridge), because we have less transistors on and probabily with less vcore.
 

bjt2

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That is a 65W Bistol Ridge apu showing 4 cpu cores and 8 gpu cores.

As I under stand it ZEN, and in particular the Summit ridge is, at top end consumer, a cpu only with 8 cores and 16 threads.
As i said in my previous post, AMD stated that a Zen core draws same power as an XV core at same clock.
There i made the calculations.
I was talking of one core turbo max. Obviously base clock should be lower.
 

bjt2

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Sep 11, 2016
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Here's what AMD's CFO recently said at an investor conference:



"Intel performance for half the price" is wishful thinking.
Would you like to answer to me, please, instead of putting my post in signature to mock me? You did that also with your previous signature, even if it was an answer to a post of mine...
 
Mar 10, 2006
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Would you like to answer to me, please, instead of putting my post in signature to mock me? You did that also with your previous signature, even if it was an answer to a post of mine...
I think your expectations of an 8 core Zen shipping at 4GHz base/4.5GHz max single core turbo are not realistic given the clocks of the leaked ES chips floating around.
 

bjt2

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I think your expectations of an 8 core Zen shipping at 4GHz base/4.5GHz max single core turbo are not realistic given the clocks of the leaked ES chips floating around.
Ok, but you are basing your statement on a first batch of early (step A0) ES, on a new process, with a new architecture. You think that retail will not be much better. I gave you "some" reason to think like me, you use the ES argument. Remember that BD ES were 2.6-2.8GHz and first retail CPU was 3.6GHz...
Only time will tell who is right...
 

nismotigerwvu

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May 13, 2004
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Honestly, everyone is just guessing at what the clocks will be like at launch. The only clocks we know for certain ONLY apply to the engineering samples. As stated above, these are ES chips on a new process, with a new architecture and may or may not have any relevance to the final silicon. Anyone claiming any certainty over the launch chips is also equally certain to be the easter bunny.
 

witeken

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Dec 25, 2013
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Ok, but you are basing your statement on a first batch of early (step A0) ES, on a new process, with a new architecture. You think that retail will not be much better. I gave you "some" reason to think like me, you use the ES argument. Remember that BD ES were 2.6-2.8GHz and first retail CPU was 3.6GHz...
Only time will tell who is right...
It's not about the ESs. It's about being a high IPC architecture, not a high frequency one.

And besides, your talk about early is quite relative. Zen is supposed to launch within 2 months, so it should already be in production right now.

I'm not saying in the future higher clocks won't become possible as they optimize the architecture, but pushing way above 4GHz shouldn't be a priority for a delayed chip that was supposed to launch in 2016. (With, as people have readily noted, a new uarch and a new process...)
 
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swilli89

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Mar 23, 2010
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I think your expectations of an 8 core Zen shipping at 4GHz base/4.5GHz max single core turbo are not realistic given the clocks of the leaked ES chips floating around.
Fastest first gen 8c Zen we will see will probably ship around 3.5ghz.
 

sirmo

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Oct 10, 2011
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I would be happy if it could OC to 4Ghz. 8 cores is not a joke. At 4Ghz with Haswell like IPC it would still be a very capable gamer, and it would absolutely rock where all 16 threads get to shine.
 

inf64

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I think there is no way that any version of Summit Ridge will ship at 4Ghz base clock. If they hit 4Ghz for ST turbo clock then it will be a huge success IMO.
I expect them to ship 3.3Ghz or 3.4Ghz base clock 8C/4C versions that might have 3.7Ghz or 3.8Ghz max. turbo clocks.
 
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sirmo

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I think there is no way that any version of Summit Ridge will ship at 4Ghz base clock. If they hit 4Ghz for ST turbo clock then it will be a huge success IMO.
I expect them to ship 3.3Ghz or 3.4Ghz base clock 8C/4C versions that might have 3.7Ghz or 3.8Ghz max. turbo clocks.
I think that would be reasonable. If they can do that while maintaining 125watts TDP, it's going to be a success.
 

bjt2

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Sep 11, 2016
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It's not about the ESs. It's about being a high IPC architecture, not a high frequency one.

And besides, your talk about early is quite relative. Zen is supposed to launch within 2 months, so it should already be in production right now.

I'm not saying in the future higher clocks won't become possible as they optimize the architecture, but pushing way above 4GHz shouldn't be a priority for a delayed chip that was supposed to launch in 2016. (With, as people have readily noted, a new uarch and a new process...)
As i said, a 19 stage int pipeline is not an high FO4 design, but a low FO4 design as BD.
I already said that high IPC does not automatically mean low clock, some post ago.
I repeat: high IPC does not imply low clocks.
 

inf64

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Mar 11, 2011
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I think that would be reasonable. If they can do that while maintaining 125watts TDP, it's going to be a success.
So far we have heard of only 65W/95W TDP brackets for HEDT. Maybe they will go for Blackest of Black versions , unlocked, 125W, shipped with AIO WC setup and running at 3.5Ghz out of the box :D. Well one can dream ;).

We also heard of some rumors about 4C/8T version nearly reaching 4790K performance level which is seriously impressive if true (no matter if it was done on stock ES clocks or OCed since 4790K runs at insanely high stock clocks anyway). And we all know how "big" the difference is between 4790K and 6700K :D
 
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KTE

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May 26, 2016
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It's matter of FO4 and clock.
You are really misinformed here.

Do you know how IPC is increased?

Do you know the process of increasing IPC increases structure SIZE and POWER?

Do you really think +40% comes free?

Do you realize how adding so many transistors in a smaller area with higher work done per cycle creates huge thermal density problems?

And how they affect the chip?


ALL of these factors are interlinked.

Forget process for now (capacitance, Vth and wire delay).


You either aim for a high IPC/low clocks design or a low IPC/high clock design.

More work per logic COSTS size/power!

There is no such thing as both possible in science!

Even when you have an excellent balance, it is about the process, the yields, and the market. Process factors are so tricky, many do not have a known cause with errors. Just 'poor reliability'.

I questioned you about Vth, capacitance and the rest of GloFo PROCESS qualities as soon as you were 'developing' them, and they still remain unanswered to date.

Show me ONE x86 desktop/server MFG that released a new uarch with MUCH higher IPC + higher core count + higher clocks + much lower power from their previous chip, in the past 15 years.

Just one.

Just design a very high FO4, high IPC CPU, then break the stages with flip flops and increase pipeline stage number. You lose something for branch miss penality, but if branch prediction is good, it's negligible. So you have an high IPC low FO4 design.
OMG.

You make all the worldd best, most intellectual researchers seem so backwards

More stages->less logic per stage=deeper pipeline=higher latencies=lower IPC=higher possible clocks

Have a read of some FO4/IPC basics because you're reasoning is non-sensical and scientifically impossible:
http://www.cs.utexas.edu/users/skeckler/pubs/isca00.pdf

Table 7 shows you exactly what I've described.

Let me be more clear:
Let's suppose BD/XV FO4 is 17 (the number is unimportant). It reaches 4.9GHz at 1.43V on the 28nm BULK and HDL libraries, with all 4 cores, 2 modules.
Now we have a Zen core, that has the same (moreless) FO4 and the same (moreless) transistors than a XV module (2 cores), half than the overclocked XV depicted above.
With the same FO4 and half transistors, a zen core is on the 14nm FF that has:
1) Less Vth
2) Less leakage
3) Less parasitic capacitance
4) More transconductance (transistor strength)
Intel has a far superior process for all intents and purposes. Why did they not see superstellar gains?

Show me where they doubled cores, increased clocks, doubled caches and structures (added much higher IPC) AND decreased power at the top of their line.

I know that with double the transistor density, heat can become a problem, but the gains are so high that we should have an increase anyway... +50% transconductance, -20% capacitance, -83% leakage, less Vth... At same frequency the power can be half per transistor... And official AMD statements of same energy cycle per core says just that.
AMD never clarified anything about WHICH Core at WHAT MHz/Voltage during WHICH workload under WHAT conditions for WHICH part of the traditional curve has the same energy per cycle.

In other words, it can really be used for nothing.

Sent from HTC 10
(Opinions are own)
 

sirmo

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Oct 10, 2011
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You are really misinformed here.

Show me ONE x86 desktop/server MFG that released a new uarch with MUCH higher IPC + higher core count + higher clocks + much lower power from their previous chip, in the past 15 years.
Sandy Bridge could both clock higher and it had a higher IPC than Nehalem. Server parts at least had more cores and it lowered power consumption as well.
 
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Sandy Bridge could both clock higher and it had a higher IPC than Nehalem. Server parts at least had more cores and it lowered power consumption as well.
Sandy Bridge's IPC gain over Westmere was, like, 10%. It also didn't clock that much higher, Nehalem in its Core i7 875K form had max single core turbo of 3.6GHz. 2600K shipped at max single core turbo of 3.8GHz.
 

itsmydamnation

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Feb 6, 2011
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It's not about the ESs. It's about being a high IPC architecture, not a high frequency one.

And besides, your talk about early is quite relative. Zen is supposed to launch within 2 months, so it should already be in production right now.
While i dont think we will see much more then 3.2/3.5 for launch (if they can squeeze a couple extra 100mhz that would always be nice) but this are just nothing words, There is nothing inherently obvious from an architecture perspective that says Zen targets a lower clock range. It will all come down physical design choices of which we know nothing about and LPP performance.
 

sirmo

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Oct 10, 2011
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Sandy Bridge's IPC gain over Westmere was, like, 10%. It also didn't clock that much higher, Nehalem in its Core i7 875K form had max single core turbo of 3.6GHz. 2600K shipped at max single core turbo of 3.8GHz.
SB had legendary OC ceiling though. Zen is also not an iterative design. We simply don't know.
 
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SB had legendary OC ceiling though. Zen is also not an iterative design. We simply don't know.
Yeah, Sandy was nice. Interestingly, as IPC went up with Ivy and beyond, that OC ceiling came down. SKL began to reverse that trend, and KBL has a good chance of finally pushing ahead of what SNB was able to do.

Intel has a super high bar to clear with Ice Lake.
 
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