AMD Family 17h (Zen) DRAM controller specifications


Junior Member
May 28, 2018
Hello everyone, I'm a computer engineering researcher and I'm currently working with DRAM fault analysis and mapping. My workstation has an AMD Ryzen 5, which uses the 17h microarchitecture (AKA Zen), so given that I'm starting pretty much from scratch I'm only trying to learn about this specific family for now.

Thankfully, I've noticed that AMD is far better than Intel at making their documentation publicly available for researchers and developers, and their BKDGs for older processor families have been incredibly helpful for my project, but unfortunately the documentation for the Zen family is still quite incomplete, with no BKDG to be found.

So my problem here is that I know how their pre-Zen DDR3 memory controllers work, but I'm still not sure how differently the Zen microarchitecture organizes its DDR4 controller. I know I'm grasping at straws here, but the official DevGurus forum is <redacted> and it's pretty much dead lately, and there aren't many other places to ask this kind of question (I've already posted this exact same text on Reddit too). Would anyone here know anything about DRAM controllers for Ryzen processors or any other Zen processor, or at least know where to find more about it?


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