Discussion AMD Cezanne/Zen 3 APU Speculation and Discussion

Page 11 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

dr1337

Senior member
May 25, 2020
311
514
106
Fresh leak out today, not much is known but at least 8cu's is confirmed. Probably an engineering sample, core count is unknown and clocks may not be final.

This is very interesting to me because cezanne is seemingly 8cu only, and it seems unlikely to me that AMD could squeeze any more performance out of vega. A cpu only upgrade of renoir may be lackluster compared to tigerlake's quite large GPU.

What do you guys think? Will zen 3 be a large enough improvement in APU form? Will it have full cache? Are there more than 8cus? Has AMD truly evolved vega yet again or is it more like rdna?
 

Insert_Nickname

Diamond Member
May 6, 2012
4,971
1,691
136
The question is, will the reduced CU count on the lower end SKUs be able to use higher memory throughput?

Even the Vega3 on my Athlon 200GE benefits a bit from running the memory at 3533MHz*, so the answer should be yes. As to whether it's worth pairing an inexpensive CPU with expensive memory would be an individuel assessment.

*@56.5GB/s it has more memory bandwidth then a GT1030. Why? Because it works... ;)
 

cortexa99

Senior member
Jul 2, 2018
318
505
136
Last edited:

dr1337

Senior member
May 25, 2020
311
514
106
That latency looks really good, lower than any zen 3 chip i've seen. Though I wonder if this is just a golden chip in the first place given its a leaked sample.
 

dsplover

Member
Nov 1, 2014
38
4
81
I’m banking on a model w/ 3.6 base.
Just wanted lower latency, single thread IPC was fine on a 3700X.
These are better designs w/ sufficient graphics.
Perfect for me.
 

zir_blazer

Golden Member
Jun 6, 2013
1,160
400
136
I don't know how these Hardware identification tools works when it comes to getting RAM specs. Besides the DIMM SPD EEPROMs, the Firmware should also build a few SMBIOS tables that are related to the RAM subsystem, and tells how many channels are, if ECC is enabled or not, etc. Given than DDR5 is still not even released and that we have been stuck with 64 Bits wide channels since SDR DIMMs introduction during the late 90's, it may be possible than it is not standarized how to retrieve channel Bit width, and that it is actually using DDR5 2 x 32 Bits per module (Which is a known DDR5 capability, using a module as either 64 Bits or 2 x 32). Hardware detection may get than it is running in Quad Channel but not that the channels are now 32 Bits wide, so it comes as 4 x 64 Bits = 256 when it should be 128.
However, there is also that infamous XBox-like APU that had Quad Channel. So it is not impossible, assuming it uses a totally new socket with a realistic increased pin budget.
 

Shivansps

Diamond Member
Sep 11, 2013
3,835
1,514
136
It is a linux kernel log and for what i know, it just reads the information provided by the VBIOS what could be wrong.

Now, Van Goth as far as i know is a replacement for the LOW END/embedded Raven2... if that thing really has a 256bit bus that may signal that AM5 is 256bit, but i dont think so. -or- that they designed all APUs with 256 bit LPDDR5.
 
Last edited:

LightningZ71

Golden Member
Mar 10, 2017
1,627
1,898
136
256 bit LPDDR5 with minimal specs gives a bandwidth that's 50% higher than the rx560 at spec. At top JEDEC spec, which is currently 51.2 GB/sec per 64 bit dimm, you get just about twice as much, at 204 GB/sec.

As a comparison...
RX570-224GB/s
RX580-256GB/s
RX5500-224 GB/s
RX6500-256 GB/s + 64MB Icache

That's a considerable amount of bandwidth. The iGPU certainly won't be starved for bandwidth.
 

NTMBK

Lifer
Nov 14, 2011
10,208
4,940
136
Could they be doing some sort of "back side bus"? 128-bit bus to the off-package memory, plus 128-bit bus to some on-package memory.
 

jpiniero

Lifer
Oct 1, 2010
14,510
5,159
136
I don't know how these Hardware identification tools works when it comes to getting RAM specs. Besides the DIMM SPD EEPROMs, the Firmware should also build a few SMBIOS tables that are related to the RAM subsystem, and tells how many channels are, if ECC is enabled or not, etc. Given than DDR5 is still not even released and that we have been stuck with 64 Bits wide channels since SDR DIMMs introduction during the late 90's, it may be possible than it is not standarized how to retrieve channel Bit width, and that it is actually using DDR5 2 x 32 Bits per module (Which is a known DDR5 capability, using a module as either 64 Bits or 2 x 32). Hardware detection may get than it is running in Quad Channel but not that the channels are now 32 Bits wide, so it comes as 4 x 64 Bits = 256 when it should be 128.
However, there is also that infamous XBox-like APU that had Quad Channel. So it is not impossible, assuming it uses a totally new socket with a realistic increased pin budget.

I think you might be right that it is a detection issue.
 

Shivansps

Diamond Member
Sep 11, 2013
3,835
1,514
136
How crazy would be to merge desktop Ryzens and TRs into one socket? Thats the only chance. Well and LPDDR5, 256bit LPDDR5 would really be good for notebooks.
 

jpiniero

Lifer
Oct 1, 2010
14,510
5,159
136
That would be the first time they do that outside semi-custom in a long time. The last time they tried a BGA-only thing it was a disaster and ended up as AM1.

I think Van Gogh is aimed at embedded edge devices that want GPU compute. A handheld gaming console is also a possibility.

Desktop I think is going to eventually get a (low end) IGP chiplet on the existing CPU products and call it a day.