lol, this is hilarious.It looks like that Van Goth has 256bit DDR5.
The DDR5 standard brings 2*32b channels per DIMM. Prior gens got just a single 64b channel. So a two-slotted Van Gogh still featurs a 128b bus - this time split as 2*2*32b and not 2*64b.
A quick googling reveals the reporting mechanism used by the AMD driver is rather simplistic. It simply reports the bus width as detected number of channels multiplied by a constant. For APUs this constant is set to 64b. Therefore this constant is not compensated for DDR5's 32b channels...
// edit: my bad, I forgot Van Gogh uses RDNA => GFX10. So that GFX9 code doesn't apply, but the DDR5 thing does.