AMD Bristol/Stoney Ridge Thread

[DrMrLordX]

All in ones have buckets of cooling capacity. They can handle a 17W CPU without even blinking. They used Stoney Ridge because it was dirt cheap, not because it was <10W.

Updated Stoney wouldn't be that much cheaper than 2018's phone SoCs or a cut-down Picasso, though. Part of why Stoney was so cheap was the small size and the aging node, but the other part was from all the prior development costs being sunk into XV. Once the baseline work on XV/Carrizo was done, it was easy/cheap enough for AMD to carry on with another XV design (Stoney Ridge). Updated Stoney would be a "leading edge" CON core project that would require them to spend precious engineering resources and cash on every aspect of the design. Unless they just did an optical shrink, which would ensure crushing mediocrity (at best) and still entail significant costs depending on the target node. Porting to GF 12nm would be cheaper.

 

[VirtualLarry]

Porting to GF 12nm would be cheaper.

This! I wonder what kind of benefits that they could garner from that. My Dell laptop that I picked up for $120 on sale at Staples, has a 1.6Ghz 6W Stoney Ridge in it. 9220e or something like that.

If they could get it to 2.0-2.2Ghz, it would be noticeably better, I feel. Well, and if they could make it dual-module, @ 10W TDP, instead of single-module @ 6W TDP, that would also make it nearly usable.

 

[Abwx]

The only advantage of a CMT design cost wise is that dies wih a single functional module can be harvested as 2C, while a 2C/4T based Zen design wouldnt allow to harvest 1C/2T dies as that s inherently a single core.

That being said it s likely that 4C/8T is AMD s projected minimal core count for next designs with harvested 2C/4T being used as low cost solution.

14nm/12nm are surely dirt cheap looking at the low end pricing, an Athlon 200GE is something like 35€ (excluding VAT) and that include the cost of a cooler and packaging, i mean selling 35$ Athlon 300U to OEMs is a better deal than those retailed Athlons...

 

[NostaSeronx]

Updated Stoney wouldn't be that much cheaper than 2018's phone SoCs or a cut-down Picasso, though. Part of why Stoney was so cheap was the small size and the aging node, but the other part was from all the prior development costs being sunk into XV. Once the baseline work on XV/Carrizo was done, it was easy/cheap enough for AMD to carry on with another XV design (Stoney Ridge). Updated Stoney would be a "leading edge" CON core project that would require them to spend precious engineering resources and cash on every aspect of the design. Unless they just did an optical shrink, which would ensure crushing mediocrity (at best) and still entail significant costs depending on the target node. Porting to GF 12nm would be cheaper.

Porting to GlobalFoundries 12LP wouldn't be cheaper, but 12FDX would be.

Steamroller/Excavator were profit positive, by Godavari AMD made their money back. The issue was that the Server/HPC field didn't get a successor product till EPYC. Killing most of top cream profit, leading to only bottom lean profit. This isn't an issue anymore, there are designs after Naples, Rome, Milan, etc. No design after is the worse thing that can happen in that field.

A core on 22FDX/12FDX isn't leading edge, its mainstream. Rather than a tunnelborer, drillrig, etc named architecture. The architecture would shift to a more aggressive less slow nomenclature. Cars for example; Miura, Diablo, etc // Bearcat, Blackhawk, etc // Virage, Vanquish, Vulcan, Valkyrie, etc. Which also denotes the change from Server/HPC-focus from the previous designs to a wholly Client-focused design.

Converting a fatter core to a slimmer core isn't particularly difficult for AMD. For example Bobcat (40nm-28nm) to Jaguar (28nm).

A new SoC or 2.5D SoC on 22FDX will and is cheaper than a new mobile focused 14nm/12nm monolithic SoC.

28BLK approximately equals 22FDX/12FDX in total cost.
28BLK to 14LPP is a 1.4x increase in total cost.
14LPP to 7FF is a 2x increase in total cost.
7FF to 5FF is a 1.9x increase in total cost.
5FF to 3NS is a 2.2x increase in total cost.

 

[DrMrLordX]

If they could get it to 2.0-2.2Ghz, it would be noticeably better, I feel.

Not good enough to compete with a hypothetical 2c/4t Picasso, though. And it would probably cost them more.

That being said it s likely that 4C/8T is AMD s projected minimal core count for next designs with harvested 2C/4T being used as low cost solution.

We haven't seen 2c/4t Zen/Zen+ from AMD yet. If AMD can harvest 2c/4t chips from failed Picasso runs, that might be their cheapest available option to replace Stoney Ridge. They could then move on to harvested 7nm parts when Renoir comes out next year.

 

[NostaSeronx]

We haven't seen 2c/4t Zen/Zen+ from AMD yet. If AMD can harvest 2c/4t chips from failed Picasso runs, that might be their cheapest available option to replace Stoney Ridge. They could then move on to harvested 7nm parts when Renoir comes out next year.

R1606G/R1505G are Raven2. The consumer versions are Ryzen 3200u/Athlon 300u.

R1606G is 100USD, R1505G is 80USD. Ryzen 3200u/300u are salvages of the 2C/4T/192SP/2xGigE die. So, I think they are in the $50-$70 range per chip.

This is in comparison to A9-9425/a9-9420e/a6-9220c which are less than $30 per chip.

These are not the same chips; https://www.amd.com/en/product/7291 Raven salvaged to 2C/4T.
& https://www.amd.com/en/product/8431 Raven2 not-salvaged with 2C/4T.

Hopefully, we can say we have seen the 2C/4T.

https://www.sapphiretech.com/en/commercial/amd-fs-fp5r <== Raven2, clearly different die than the V1000; https://www.ibase.com.tw/english/ProductDetail/EmbeddedComputing/MI988 , https://www.sapphiretech.com/en/commercial/amd-ipc-fp5v-1ge

With that Atari VCS went from Bristol Ridge to Raven2. This implies from a direct sale perspective AMD to Atari that Raven2 costs the same as Bristol Ridge. Raven2/Bristol equals $x cost. While Stoney which costs $y is less than Bristol, and is also lower than Raven2.

 

[NTMBK]

With that Atari VCS went from Bristol Ridge to Raven2. This implies from a direct sale perspective AMD to Atari that Raven2 costs the same as Bristol Ridge. Raven2/Bristol equals $x cost. While Stoney which costs $y is less than Bristol, and is also lower than Raven2.

Flawed logic- what AMD can extract from a customer does not necessarily bear any resemblance to AMD's costs. For example the Bulldozer/Piledriver family had enormous die sizes while failing to be competitive with Intel products, meaning that AMD had to price them low (with rubbish margins) in order to be able to shift them.

 

[Abwx]

We haven't seen 2c/4t Zen/Zen+ from AMD yet. If AMD can harvest 2c/4t chips from failed Picasso runs, that might be their cheapest available option to replace Stoney Ridge. They could then move on to harvested 7nm parts when Renoir comes out next year.

2C/4T Athlon 300U and R3 3200U laptops are available for some time :

https://geizhals.de/?cat=nb&xf=6751_21~6751_24~9690_Picasso

 

[NostaSeronx]

Flawed logic- what AMD can extract from a customer does not necessarily bear any resemblance to AMD's costs. For example the Bulldozer/Piledriver family had enormous die sizes while failing to be competitive with Intel products, meaning that AMD had to price them low (with rubbish margins) in order to be able to shift them.

It does actually bare resemblance to AMD's costs. Bulldozer/Piledriver family had less xtors, and a less complex process than Intel. Which continued even with Steamroller/Excavator. AMD usually caused GlobalFoundries to run at a loss to absolute profit. Other customers of the PDSOI nodes would offset the loss over time.

28BLK to 22FDX should follow the asymmetrical cost expectation. Where as 14nm to 7nm does indeed follow cost expectations.

Went from AMD paying less with the "S" plan to AMD paying more with a marked up Samsung Node.

 

[NTMBK]

It does actually bare resemblance to AMD's costs. Bulldozer/Piledriver family had less xtors, and a less complex process than Intel. Which continued even with Steamroller/Excavator. AMD usually caused GlobalFoundries to run at a loss to absolute profit. Other customers of the PDSOI nodes would offset the loss over time.

28BLK to 22FDX should follow the asymmetrical cost expectation. Where as 14nm to 7nm does indeed follow cost expectations.

Went from AMD paying less with the "S" plan to AMD paying more with a marked up Samsung Node.

Then explain why AMD's margins were terrible all through the Bulldozer period, and why they kept losing money.

 

[NostaSeronx]

Then explain why AMD's margins were terrible all through the Bulldozer period, and why they kept losing money.

AMD moved towards low volume Bobcat and Jaguar. The only good products were Zambezi, Vishera, Komodo, Trinity, Kaveri, etc. The major loss was Computing Solutions which had no product after Interlagos, Abu Dhabi, Warsaw which of course saw price gouging as they were more mature. AMD saying they don't want to buy 32nm PDSOI in the 2012 year, because canned Komodo, Terramar, Sepang could also have caused the losses. We the customers would have seen the problem octo-core die(2009/2010/00h-0fh) to the deca-core die with the extended fixes(2010/2011/20h-2fh).

The same can be said for the Zen period, why isn't there a massive rise of Net income and Operating/Net margins. AMD should be successful, but apparently they are having employees jumping ship.

Historically, what is called Fab 7 and Fab 1 Module 2 were originally both were going to 32nm(28nm) bulk/22nm(20nm) bulk;
"In September 2008, our company announced the development of a comprehensive 32nm and 28nm SOC design platform based on high-k metal gate technology from the IBM-led joint-development alliance.

2009 Planned Research and Development Expenditures - We expect R&D expenditures in 2009 to remain essentially flat compared to $178 million in 2008. The investment is intended to fund primarily the development and qualification of 32nm process technology, including costs associated with capital investment in leading-edge semiconductor tools."

Basically, when GlobalFoundries bought Chartered they would have gotten three fabs that could do 32nm bulk or 28nm bulk: Fab 1, Fab 8, Fab 7. What they could have done as they currently are doing with the 22FDX process. More fabs at a given process equals lower cost across various consumers. There is also cross fab fixes which was how Malta corrected Dresden's 32nm PDSOI. Now imagine with four fab teams; Chengdu, Dresden, Malta, Singapore and main team Santa Clara scanning for issues on a single node.

Family 15h = 2011-2019+ (No RIP)
Family 14h = RIP
Family 16h = RIP
Family 17h = Soon to be RIP
Family 19h = Will probably still be next to 15h.

Ideally, we would want after Stoney Ridge there to be an architecture and a SoC template that can last from 2020 to 2030. Hoping on to the FDX train from 22FDX(post-2020) to 3FDX(pre-2030).

 

[amd6502]

We haven't seen 2c/4t Zen/Zen+ from AMD yet. If AMD can harvest 2c/4t chips from failed Picasso runs, that might be their cheapest available option to replace Stoney Ridge. They could then move on to harvested 7nm parts when Renoir comes out next year.

Yes we have, Nosta posted a die of FP5 product that was about half size of Raven. We now refer to this native dual core as Raven2. It seems it probably is 14nm but not 100% sure on that.

The only advantage of a CMT design cost wise is that dies wih a single functional module can be harvested as 2C, while a 2C/4T based Zen design wouldnt allow to harvest 1C/2T dies as that s inherently a single core.

I don't see why 2c/4t Raven2 cannot be salvaged as 1c/2t. In fact, such an APU would be perfect for ULP like 6W and maybe even lesser TDP.

SMT these days has gotten so efficient that a wide core SMT core can now keep up with an XV module in multithread. So, a 1c/2t Zen would be better performance than Stoney. Similar MT maybe, but that much better ST should make overall performance difference noticable.

As far as die harvested dozers, they only enabled fully functional modules. So quadcores would go down to dual cores. This was is the simplest way to die harvest. It may not have been the only way. There probably were some defects where they could in theory have symmetrically disabled an integer core on each module , which would have freed up shared resourced like L1i (and the shared decoders for pre-steamroller generations). Probably just wasn't worth the extra complication for any miniscule improvement. By the way, AM3+ and I think also some FM2+ boards allowed users to disable one core per module (i.e., turn off CMT), so we know it's no issue to run with one core per module.

I would think that integer core defects are so rare on Stoney that they will never offer something like an embedded market die salvaged 1c/1t APU.

On Zen, I'm surprised we haven't seen anything like a 3c/6t APU or CPU. I would love see something between 3200g and 3400g; something with modest frequencies but higher thread count than the 3200g.

 

[DrMrLordX]

2C/4T Athlon 300U and R3 3200U laptops are available for some time :

Oh! I didn't even know the 3200u existed. Foolish me. Then that would be the most-obvious replacement for Stoney Ridge. Done deal, the chip already exists. And it can be configured for a cTDP as low as 12w which means you can stick it in an AiO without difficulty. Athlon 300u should work just as well (TDP of 15W is maybe a bit toasty for some AiOs, but as @NTMBK indicated, 17W is not a problem).

So it is official: there is no need for future revisions of Stoney Ridge. Or anything CON-based.

The main challenge for AMD now is to get Stoney Ridge garbage out of the channel and out of the warehouses so that OEMs will stop damaging their brand by selling them to unwary customers.

Nosta posted

I only have a few people on ignore here. He is one of them.

edit: and now you know why!

 

[NostaSeronx]

Oh! I didn't even know the 3200u existed. Foolish me. Then that would be the most-obvious replacement for Stoney Ridge. Done deal, the chip already exists.

Missing vital information. Stoney Ridges die costs $10-ish in the most mature volume. While, Raven2 costs $30-ish with a mature yield, which is the same price as Bristol. Bristol technically even with the shrink of Raven2 is a couple cents(hundredths position, if not tenths) cheaper.

So it is official: there is no need for future revisions of Stoney Ridge. Or anything CON-based.

However, Stoney is cheaper than Raven2. Anything con-based would have superior performance/power curve down the line. 22FDX/12FDX are better than 14LPP/7FF respectively. This is exacerbated as FDSOI in lesser tracks actually are faster than the Fin-depopulated tracks. Digital 8T FDSOI is faster and consumes less than any 7.5T FinFET. Digital 7.5T FDSOI is faster and consumes less than any 6T FinFET.

The main challenge for AMD now is to get Stoney Ridge garbage out of the channel and out of the warehouses so that OEMs will stop damaging their brand by selling them to unwary customers.

I'm pretty sure customers prefer not paying absurd prices without getting a Celeron N4000.

A single high-performance dual-core CMT module can replace four low power cores. This is seen with Carrizo-L to Stoney Ridge;

A9-9410 vs A8-7410, A9-9420/A9-9425/A9-9435 not included.

However, Jaguar/Zen/Goldmont(+) are all client processors first. With Excavator retaining Bulldozer's Server/HPC first, then client last mentality. Excavator with Steamroller is solely mobile optimized with physical redesign, some architecture tweaks(not enough to be a new architecture, still 15h), and a 28nm process.

22FDX with a new architecture that is still CMT and retains frequency advantage. Will for a change be better suited than Excavator is in those client markets. Equating to a faster architecture, not a slower one than Zen-successors/Goldmont-successors.

 

[Abwx]

Missing vital information. Stoney Ridges die costs $10-ish in the most mature volume. While, Raven2 costs $30-ish with a mature yield, which is the same price as Bristol. .

An Athlon 200GE, wich is about 200mm2, is sold 35€ (excluding VAT) in Germany, and that include the cooler, packaging, transportation to Mindfactory as well as said reseller margin, so the die cost is no more than 15$.

At your made up 30$ this would put the waffer cost at more than 8000$, that s as much as TSMC s 7nm node waffers, so much for missing vital information.

 

[NostaSeronx]

An Athlon 200GE, wich is about 200mm2, is sold 35€ (excluding VAT) in Germany, and that include the cooler, packaging, transportation to Mindfactory as well as said reseller margin, so the die cost is no more than 15$.

At your made up 30$ this would put the waffer cost at more than 8000$, that s as much as TSMC s 7nm node waffers, so much for missing vital information.

Raven is ~$70, and Athlon 2xxGE is a limited production product. Salvaged products can cost less than the value calculated, if most of the products are above the processed cost.

It isn't detailed if the values are for end-users(people buying the finished product) or the values are for the ones who purchased the wafers. The best assumption is that it is the minimum value which the chip should be sold.

$70 USD => $170 USD 2400G, $99 USD 2200G, etc. <== These are probably cheaper than Ryzen 2700u/2500u and the Ryzen embedded products.

 

[Abwx]

Raven is ~$70, and Athlon 2xxGE is a limited production product. Salvaged products can cost less than the value calculated, if most of the products are above the processed cost.

It isn't detailed if the values are for end-users(people buying the finished product) or the values are for the ones who purchased the wafers. The best assumption is that it is the minimum value which the chip should be sold.

$70 USD => $170 USD 2400G, $99 USD 2200G, etc. <== These are probably cheaper than Ryzen 2700u/2500u and the Ryzen embedded products.

Did you read what i posted..?.

Are you going to insist that a 14/12nm waffer cost is 8000$+.?.

TSMC stated that their 7nm waffers are now significantly below 10 000$, wich put them at the price you re using for your flawed 14/12nm "estimation", at the end you are deliberatly throwing fairy taled numbers just to keep supporting a FDSOI illusory design, btw this thread is already 3.5 years old, 28nm Stoney and Bristol Ridge keep being sold and apparently there s no shrink in sight, and ever if there were one it would still use the highest performing node at GF.

FDSOI as implemented by GF is or for lower than 100mm2 dies, at 100mm2 a lot of the benefits are already gone, among others speed, wich is a no go for AMD.

 

[NostaSeronx]

If there were one it would still use the highest performing node at GF.

Which is currently the FDX set.

FDSOI as implemented by GF is or for lower than 100mm2 dies, at 100mm2 a lot of the benefits are already gone, among others speed, wich is a no go for AMD.

28nm Stoney Ridge = 125 mm squared
22FDX 2D = less than or equal to 125 mm squared
22FDX 2.5D = two dies less than or equal to 70 mm squared.

FDSOI has better low and high voltage statistics compared to 28nm. The 22FDX 8T design would be faster than the 7.5T(12LP) and 6.75T(11LPP).

28LPP -> 28LPH -> 28FDS = Lowest to Greatest performance.
28FDS = 28HPP
28FDS Gen2 > 28SHP/28A/28HPA
GlobalFoundries comment on FDSOI is that it is far better than their own "HP" processes. That was all the way back in 2013 after they got the FDSOI license.

28nm to 22FDX total per-die savings for high performance is around 20%. 28SHP-cost * 4/5
12FDX versus 12LP total per-die savings for high performance is estimated to be 50% by 2022. (Earlier is up to 60% or more.) 12LP-cost * 1/2 to 2/5.

 

[Abwx]

GlobalFoundries comment on FDSOI is that it is far better than their own "HP" processes. That was all the way back in 2013 after they got the FDSOI license.

I guess that you are completely out of reality by stating the contrary to what GF s Patton s stated, that is, that 14nm not even 12nm, was for designs that required not only higher areas but also higher perfs than
FDSOI :

I did want to make one more core comment at 22FDX: I think one thing that might not be clear is that our 22FDX was specifically optimized for the IoT/mobile/automotive space

https://www.anandtech.com/show/1243...ew-with-dr-gary-patton-cto-of-globalfoundries

 

[NostaSeronx]

GlobalFoundries' Gary Patton is most likely biased towards FinFETs. Since, he was at the top of Dev/Research for 14nm/10nm/7nm FinFETs at IBM. As far as I can tell the partnership between IBM/STMicroelectronics FDSOI wasn't that large. As he was heavily biasing research towards FinFETs.

GlobalFoundries fails to do what by itself => FinFETs. What is his legacy as CTO since pivot => No 7nm FinFETs. What has been nearly irreversibly harmed by this strategy? FDSOI.

FDSOI checklist of shuffled to later implementations;
Gate-first MIPS successor...
Strained SOI...
Improved BEOL...

 

[Shivansps]

Look, the Athlon 300U and Ryzen 3200U already more than doubles passmark score of the A6-9220/9225 at the same TDP, there is really NO WAY, and even if there was it is better to re-use picasso than putting money on another product.

They need to double the cores while maintining clocks and tdp in order to more or less match 2C/4T Picasso MT at the same TDP. And Picasso is already running on a old node by now. That just pointless.

 

[DrMrLordX]

They need to double the cores while maintining clocks and tdp in order to more or less match 2C/4T Picasso MT at the same TDP. And Picasso is already running on a old node by now. That just pointless.

They would actually need higher clocks, or more IPC. Picasso's ST performance annihilates even the A9-9425.

 

[NostaSeronx]

Look, the Athlon 300U and Ryzen 3200U already more than doubles passmark score of the A6-9220/9225 at the same TDP, there is really NO WAY, and even if there was it is better to re-use picasso than putting money on another product.

They need to double the cores while maintining clocks and tdp in order to more or less match 2C/4T Picasso MT at the same TDP. And Picasso is already running on a old node by now. That just pointless.

Ryzen 3200u(Q2 2019)/(2.6 to 3.5) =
nT:4937
1T:1740

A9-9425(Q2 2018)/(3.1 GHz to 3.7 GHz) =
nT:2533
1T:1497

A9-9420e(Q2 2018)/(1.8 GHz to 2.6 GHz) =
nT: 1904
1T: 1124

A near 1 GHz increase lead to an average between 60 samples and 22 samples from 1124 to 1497 is 373 pts.

If AMD added 1 GHz again, and had a similar change between Steamroller(13T/28nm) to Excavator(9T/28nm). We can simply add the 373 pts to the A9-9425, which will come out to 1870 pts. However, the biggest opportunity for AMD is not a revision of 15h, but a new architecture.

Certain designs can get a full-esque shrink from 9T-28nm to 8T-22nm. If we assume there is a shrink as the FPU scheduler/FMAC shrunk 38%/35% from 13T/28 to 9T/28. Another shrink, up to 40% would allow for certain special things to happen to the FMACs. The only other numbers were of the I-cache control/35% shrink, if a 15h revision it could probably allow for 128 KB L1i on 22FDX. The only reason to go that route is to replace Zen, which shouldn't be the purpose of 22FDX/12FDX.

It is better to have something like the below, than a continuation of 15h.
32 KB L1i 10T/2 x 16KB L1d 10T/512KB L2 10T/8T <== 10T for short channel effect immunity, reduced delay, reduced power consumption, reduced area, etc.
3 ALU/3 AGU with a new scheduler, distributed physical register file <== slightly more IPC, the dPRF should reduced delay by 10%? and power by 20%? and area 40%.
FPU could do split with each core gets 2x FADD+2x FMUL or 4x 128b FMAC in a single unit. The removal of the MMX is key, to the potential focus towards mixed-point calculations. At least, half of the FPU will be fixed point and the other half floating point. With enhancements towards fixed + floating calculations and fixed <-> floating conversions. With bfloat on the floating side and integer mantissas + float exponent on fixed point side.

Pure FMAC/Single Unit = Highest efficiency // Best option. <-- this would boost it on 1T.
FMUL+FADD/Two unit = Highest speed // Second best option. <-- this would boost it on nT.

There is also mixed track height; 8T/22nm for critical paths with LVT, 7T/22nm for non-critical paths RVT/HVT. Which can further improve density and power, while negligible to no performance loss. There is definitely enough extremely modern optimizations that can be done to allow higher IPC and higher frequency. While reducing area utilization and power consumption. This all on a node that is similar in price to current gen 28nm, and lower development costs than 14nm onwards.

 

[Abwx]

IPC is roughly 50% better with Zen+, we wont even talk of Zen 2.
To get the same ST perf rom XV require 2.5x the power albeit at much lower transistor count, but still, that s a limited design in comparison as it has no room fo better perfs unless a radical redesign is done, at wich point using even Zen+ would be way more efficient in all fronts, including the financial one.

Beside no mention is made, even it was posted in this forum, that there s a native 2C/4T Raven Ridge, one has to wonder why they released this SKU if it were to be replaced by a chimeric FDSOI based Stoney Ridge.

 

[NTMBK]

Family 15h = 2011-2019+ (No RIP)
Family 14h = RIP
Family 16h = RIP
Family 17h = Soon to be RIP
Family 19h = Will probably still be next to 15h.

You're living in a fantasy world. 15h has not had a new CPU design since Carrizo, which launched in 2015! It's dead! It isn't coming back!

AMD has Zen on its roadmap all the way out to Zen 4. They don't have a single Construction core on any of their roadmaps. Give it up already. CMT lost.