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AMD Bristol/Stoney Ridge Thread

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amd6502

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A4-9120C 2.4 GHz/6W => ____C ~3.2 GHz/~4W
A6-9220C 2.7 GHz/6W => ____C ~3.6 GHz/~4W
There is more to it as well, as the FDSOI transistors have better leakage characteristics, increased lifespan expectancy, lower variability, etc.
That would be quite awesome. They really should offer more than 2 threads though. With the density shrink, will the die just be smaller or do you expect them to add cores or features?
 

NostaSeronx

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That would be quite awesome. They really should offer more than 2 threads though. With the density shrink, will the die just be smaller or do you expect them to add cores or features?
The Stoney Ridge migration isn't a shrink. It is the same design as before just more compatible with Raven2.

Picasso -> Raven2 -> 22FDX
Renoir -> Dali -> 12FDX

In particular launch pattern, earliest to later.

22FDX should be 1:1 with Stoney Ridge. 2c/2t, 3CU/192sp, 1x UVD, 1x VCE, 1x64 DDR4-2400?, etc.

12FDX CPU should be 15h 40h-4Fh but with Matisse's/Vermeer's common I/O chiplet. (A 15h 00h-2Fh cache architect is the lead L3(SRAM?) architect for this project)
12FDX APU should continue 30h-3Fh, 60h-6Fh, 65h-6Fh trend of 4C/4T, 8CU/512SP. (A leading FDSOI IoT/ULP cache architect is doing CPU/GPU memories(L1, L2, register files, roms, etc) for this project)
//November 2018 for the APU, March 2019 for the CPU.

FDSOI is only cluster-based multithreading at AMD/GlobalFoundries.
 
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VirtualLarry

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I just upgraded my Dell with the Stoney 9220e APU laptop, from the factory 4GB DDR4-2400 DIMM, to an 8GB DDR4-2667 DIMM, that appears to be running at 2400. (At least, the BIOS and Windows say 1200, so I'm not sure. There's no place in the BIOS to adjust DRAM clock, it's very spartan, seeing as it's from Dell on a consumer laptop.)

It sure could use double the number of cores, though. CPU-wise, it's basically nearly almost like using a single-core, it gets a bit bogged down multi-tasking.
 

NTMBK

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I just upgraded my Dell with the Stoney 9220e APU laptop, from the factory 4GB DDR4-2400 DIMM, to an 8GB DDR4-2667 DIMM, that appears to be running at 2400. (At least, the BIOS and Windows say 1200, so I'm not sure. There's no place in the BIOS to adjust DRAM clock, it's very spartan, seeing as it's from Dell on a consumer laptop.)

It sure could use double the number of cores, though. CPU-wise, it's basically nearly almost like using a single-core, it gets a bit bogged down multi-tasking.
Wow, what a waste of an 8GB SODIMM. That laptop is a turd Larry, stop throwing away money on it!
 

VirtualLarry

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Wow, what a waste of an 8GB SODIMM. That laptop is a turd Larry, stop throwing away money on it!
C'mon. It may be a 'turd', but with an 8GB SO-DIMM (DDR4), it's at least a usable turd. Which is an improvement. Still, I only spent like $34-35 on the 8GB DDR4 SO-DIMM, so the laptop was $120 + tax, still fairly inexpensive for a laptop with a psuedo-1080P screen and 8GB of RAM. The 32GB eMMC on this laptop sucks badly though, I really wish that Dell had soldered in the SATA port jack, would have loved to just drop a SATA SSD in there too, would have made it WORLDS better. The BIOS and Device Manager report a SATA AHCI port is active. Just needs to be soldered in, apparently.

Edit: Yeah, I do have a microSD in there too, for my personal files.
 

ao_ika_red

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I just upgraded my Dell with the Stoney 9220e APU laptop, from the factory 4GB DDR4-2400 DIMM, to an 8GB DDR4-2667 DIMM, that appears to be running at 2400. (At least, the BIOS and Windows say 1200, so I'm not sure. There's no place in the BIOS to adjust DRAM clock, it's very spartan, seeing as it's from Dell on a consumer laptop.)

It sure could use double the number of cores, though. CPU-wise, it's basically nearly almost like using a single-core, it gets a bit bogged down multi-tasking.
The exact reason why I never recommend any netbook based on SR chip. Thankfully, there are plenty N5000 laptops and on some occasion, you can get i3 or 2200u as well.
 

VirtualLarry

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The exact reason why I never recommend any netbook based on SR chip. Thankfully, there are plenty N5000 laptops and on some occasion, you can get i3 or 2200u as well.
Well... yeah. I would have much preferred an N5000, with four REAL cores. And one with a real 2.5" SATA bay / port, to put a REAL SATA SSD in.

But that probably would have cost me $250, maybe $300 with a 1080P screen. And I did end up with AMD graphics, and a DDR4 (single-channel) platform.

All in all, it's mostly "disposable", which is how you should consider those netbooks with non-user-replaceable batteries, and eMMC storage. I don't regret the purchase, though.
 

amd6502

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I just upgraded my Dell with the Stoney 9220e APU laptop, from the factory 4GB DDR4-2400 DIMM, to an 8GB DDR4-2667 DIMM, that appears to be running at 2400. (At least, the BIOS and Windows say 1200, so I'm not sure. There's no place in the BIOS to adjust DRAM clock, it's very spartan, seeing as it's from Dell on a consumer laptop.)

It sure could use double the number of cores, though. CPU-wise, it's basically nearly almost like using a single-core, it gets a bit bogged down multi-tasking.
Unfortunately i don't think one can get it to run at 2667, and unless the ram has multiple XMP profiles, it will take a tiny hit with a tad longer CAS latency; no way to adjust timing for OEM laptop mainboard.

I've been using an A6-9225 (15W tdp) as windows machine (www and simple legacy CAD). It browses fine, though noticably slower than my A12. Fine for email and news.

Your A6 (medium bin) could use about 20% faster boost; seems more tablet material than laptop APU. Top binned 6W A9 is probably the minimum for decent performance. Or high to medium bin 10W; the A9-9400 is a good SKU that is laptop material.

http://www.cpu-world.com/Compare_CPUs/AMD_A6-9220e,AMD_A6-9225,AMD_A9-9400,AMD_A9-9420e,AMD_A9-9425/

If Raven2 gets 1c/2t die salvage they may become 6W parts and could outperform some of these Stoneys; maybe generally will.

It could really use the fdx efficiency and wattage gains Nosta talks of.

The Stoney Ridge migration isn't a shrink. It is the same design as before just more compatible with Raven2.

Picasso -> Raven2 -> 22FDX
Renoir -> Dali -> 12FDX

In particular launch pattern, earliest to later.

22FDX should be 1:1 with Stoney Ridge. 2c/2t, 3CU/192sp, 1x UVD, 1x VCE, 1x64 DDR4-2400?, etc.
It sounds plain vanilla but better than nothing I guess.

IMHO a 2+2 big-little with jaguar would have been the way to get best of both world for good MT, goot ST, and good near idle wattage.
 
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ao_ika_red

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IMHO a 2+2 big-little with jaguar would have been the way to get best of both world for good MT, goot ST, and good near idle wattage.
Having 4 puma++ cores in 12nm would be better on $200-300 netbook. Add that with 4 NaviCU would be beyond imagination.
 

amd6502

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Having 4 puma++ cores in 12nm would be better on $200-300 netbook. Add that with 4 NaviCU would be beyond imagination.
These cores are very efficient at lower frequency and p-states. These puma (carizzo-L) APUs never made it to 6W (nor 10W I think) and this is true for the salvaged dual core soc's too. XV got all the expensive high efficiency improvements. Also, Carrizo-L had GCN 1.1 while Carrizo had GCN 1.2 They are very low transistors count relative to modern cores are perfect candidates for major revision, such as adding coarse grain multithread (MT2) so that they can take over the computing for a 4 thread mini-CCX at the lowest p-states.
 

NostaSeronx

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16h (Jaguar) has already been upgraded into 17h (Zen). There is no reason to support continued Jaguar on newer nodes.
15h (Bulldozer) has not been upgraded into a later family. With the SKUs; A6-9220C, A4-9120C... there is enough reason to have sequel parts.

What I expect/want is IoT/ULP, μCMT, Vbb-aimed OC/boost;
IoT/ULP ex: Removal of big; branch predictor, L1i, L2 cache for more efficent smaller branch predictor, L1i, L2, etc.
Micro-CMT; Push the core duplication down to L0, 1x L1i 32KB + L1d 32KB (Module resources), with 2x 4-8 KB L0i(+uop caches)/L0d (Core resources). The FPU if separate would only be ported to module resource(single L1d), rather than core resources(two L0d caches).
Forward body bias can boost with negligible aging effects over voltage scaled frequency. The first step is to undervolt, then to increase forward Vbb which lowers Vt increasing Fmax at the lower voltage, etc.
 
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amd6502

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16h (Jaguar) has already been upgraded into 17h (Zen). There is no reason to support continued Jaguar on newer nodes.
15h (Bulldozer) has not been upgraded into a later family. With the SKUs; A6-9220C, A4-9120C... there is enough reason to have sequel parts.

What I expect/want is IoT/ULP, μCMT, Vbb-aimed OC/boost;
IoT/ULP ex: Removal of big; branch predictor, L1i, L2 cache for more efficent smaller branch predictor, L1i, L2, etc.
Micro-CMT; Push the core duplication down to L0, 1x L1i 32KB + L1d 32KB (Module resources), with 2x 4-8 KB L0i(+uop caches)/L0d (Core resources). The FPU if separate would only be ported to module resource(single L1d), rather than core resources(two L0d caches).
Forward body bias can boost with negligible aging effects over voltage scaled frequency. The first step is to undervolt, then to increase forward Vbb which lowers Vt increasing Fmax at the lower voltage, etc.
With the improzed faster L2 (from Zen) those tiny L1 cache would be interesting.

The L0 could also be used to give each module two background tasks that are run with coarse grain multithread. (Switch on L2 miss, or after timeout switch stochastically on L1 miss.) Give it the single FPU and let the FPU boost at or near fmax while integer cores run at around half frequency whenever the FPU gets saturated. A module would get great utilization with 2+2 threads. Single thread would hurt a little bit from the mini-sized L1 though (For iots and craptops maybe that's okay).

I guess such a 5W Stoney++ would compete where Raven2 2c/4t could not. Sub 6W mobile and iots; kind of right in acorn's backyard.
 

amd6502

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16h (Jaguar) has already been upgraded into 17h (Zen). There is no reason to support continued Jaguar on newer nodes.
15h (Bulldozer) has not been upgraded into a later family. With the SKUs; A6-9220C, A4-9120C... there is enough reason to have sequel parts.

What I expect/want is IoT/ULP, μCMT, Vbb-aimed OC/boost;
IoT/ULP ex: Removal of big; branch predictor, L1i, L2 cache for more efficent smaller branch predictor, L1i, L2, etc.
Micro-CMT; Push the core duplication down to L0, 1x L1i 32KB + L1d 32KB (Module resources), with 2x 4-8 KB L0i(+uop caches)/L0d (Core resources). The FPU if separate would only be ported to module resource(single L1d), rather than core resources(two L0d caches).
Forward body bias can boost with negligible aging effects over voltage scaled frequency. The first step is to undervolt, then to increase forward Vbb which lowers Vt increasing Fmax at the lower voltage, etc.
Zen and Jaguar family are very different. Zen likely was inspired by both 15h and 16h (granted though, with a lot more 16h designers and engineers contributing to Zen than 15h ones).

So it does turn out the L1i's are trending to be way downsized, with Zen2 halving L1i to 32kB/core. I think the L2 could be backing it up as a buffer or L1i eviction cache. Your micro-cmt proposal could hold water and would seem in conjunction with Zen2 development.

Some rumors had been of Zen3 being SMT4 capable. This could have huge application to mobile and battery life... if threads/cores can be hotswapped, with cores being able to power down while switching SMT mode preserves the logical number of cores. Eg., imagine a 4c/4t Ryzen 4300u that has only one core (SMT4), two (SMT2), or four active cores (SMT0) depending on its CCX p-state. Running in single-core mode could give it very good near idle wattage.

Another way to go even lower would be to revive the low power architecture with a /next gen Jag, and use it in a big.little fashion like mentioned above.

Why 16h and not 15h?

Although XV eventally surpassed Puma+ in efficiency it was only because development/funding of 16h completely dried up. XV has maxed out in perf without a new node and/or a complete redesign that would totally change its structure, while a NG jag redesign wouldn't need to be so radical and would be about as incremental as going from PD to steamroller.
 
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NostaSeronx

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We have two SKUs left in the Stoney Ridge library left which are A9-9435 and A6-9235.

The three possibilities after the above is... continuing from previous posts.
1. 22FDX APU(no chiplets)
2. 22FDX IOD(MC_Bufer,GMC_Buffer,GFX_PCIe,GPP_PCIe,USB,DCN,etc) + 12FDX ACD(CPU/GPU/MMN w/ package cache(shared/unified L3))
3. Both with 1st first and 2nd second.

My expectations thus speculation on the 22FDX at this moment; New cluster-based multithreading microarchitecture and up-ported lightweight RDNA.
With that the 12FDX; Enhanced version of the above and more cores via more modules and possibly heavyweight RDNA with more WGPs/CUs.

New CMT architecture => Smaller cores and module from Excavator, with two things lower leakage thus lower power, and higher frequency at lower watts.
The best average is 45% higher frequency to 45% lower power at 45% less area on logic side.
If capable 125 mm squared to ~90 mm squared is like 400+ good dies to 600+ good dies. Even with the worst yields on GlobalFoundries 22FDX proven dies(less than 5 mm to greater than 115 mm squared). Which are ~84% good yields is 500+ good dies with a die of approximately around 90 mm squared.

1st APU is direct successor to Stoney Ridge. 64b, same IO, same core count but new module/core, same gpu count but new gpu architecture.
2nd APU is an indirect successor to Raven2 and shares the IOD with the direct successor 7nm+ Accelerated Complex die; CPU cores, GPU cores, Multimedia cores(VCN(Video Decode/Encode) and ACP(Audio Decode/Encode)).

The other first is 22FDX IOD + 22FDX ACD. Sneaking into the Raven2/Dali platform. Same IOD in both 1st and 2nd, different ACD between the two. With the possibility of the 7nm+ ACD using the same 22FDX IOD. The 22FDX IO die has less I/O compared to the 12LP IO die. 22FDX IOD compares directly with Raven2 IMC/FCH. This directly changes the 1st calc of 90 mm squared, since it is two dies rather than one.

IOD 22FDX; (guess)
x4 GFX / x4 GPP / 128-bit(ECC +16(DDR4) or +32(DDR5)) memory controller / Single IF connection } North I/O Hub
x2 NVMe / x2 SATA / eMMC / 1G Ethernet / x4 USB 3.x/ Misc } South IO Hub
3x DP/HDMI/eDP or PCIe } Display Hub
Arm Cortex-M35P? } Security Hub
 
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amd6502

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I think MCM is not so good for low end. It's also nice to avoid for mobile.

But creating an IO Hub for Zen2 and beyond with FDX has always seemed like a possibility. But I think the next IO Hub will have integrated GPU, so probably would be Vega (6 to 8 CU). Unless they port Navi to FDX.

A9 9435 (3.1-3.7 GHz) is binned above 9410 (2.9/3.5), so probably a medium to med-hi bin.I think 9410 is a med-lo bin, and it's smart to use the lower binning for 25W all in ones or preferrably bottom end SFF desktops (where it's easier for the user to pull the board for an upgrade once it outdates ina few years). Today, browsing on XV dual core in mid 3.5 ghz is really quite good. This is quite good for the OEM's; it's got to be dirt cheap (and they're also fond of the users putting these machines in a dummster and buying a replacement in a few short years).

We were discussing one 95%+ fake "leak" on the Zen3k thread, involving a mini-sized Bristol ridge die (~110mm2), ported to 28FDX without the GPU. The supposed leak claimed OC to 5ghz and beyond and stock pretty close to 5ghz. https://forums.anandtech.com/threads/speculation-ryzen-3000-series.2558009/post-39875852 such a product would be great for a low cost (sub $30!!) AM4 zen alternative, together with a BGA version for embedded/automotive and lower end oem SFF gaming desktops when combined with a low end 1080p dGPU (eg rx 560 and somewhat above). So even though the leak was probably fake, the idea is brilliant.
 
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NostaSeronx

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The A9-9435/A6-9235 are not out as of yet. (No geekbench, products, etc)

1st: A9-9400(2.4/3.2)@10w/A6-9200(2.2/2.8)@10w
2nd: A9-9410(2.9/3.5)@25w/A6-9210(2.4/2.8)@15w
3rd: A9-9420(3/3.6)@15w/A6-9220(2.5/2.9)@15w
4th: A9-9425(3.1/3.7)@15w/A6-9225(2.6/3)@15w

The most likely specs for the CPU would be;
5th: A9-9435(3.2/3.8)@15w/A6-9235(2.7/3.1)@15w

...
The chiplet design on the package would allow for the best integration. Smaller dies would also negate the lower performance from potentially lower drive current. Basically, also having none of the small FinFET/Ox-Fin/Stacked Nano_x die problems either. (Thermal coupling, vertical self heating, capacitance/resistance from 7nm and shorter BEOL, etc) Which means the frequency/voltage barrier on 22FDX/12FDX is a bit higher than 14LPP/12LP/7FF/3NX. Meaning higher voltage in the AVFS range is more stable, and has easier access of higher frequency with 22FDX/12FDX compared to 14LPP-onward for High Performance.

28BLK -> 22FDX => Shorter channels, steadier LVT(higher Vmax), faster RVT(higher Fmax), lower leakage and variability, and in between Q4-19 and Q2-20 22FDX should start to cost less. If it doesn't cost less currently, it will then.
 
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amd6502

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A6-9235(2.7/3.1)@15w
That's a good guess.

9425 (3.1/3.7@15W) is top bin. 9435 (3.1/3.7@25W? which would be 200mhz above 9410) I suspect is somewhat lower binned; same freq as 9425 but higher wattage i suspect, and probaly can sustain closer to top boost longer. https://www.newegg.com/dell-inspiron-24-3475-business-desktop-workstation/p/1VK-0001-2NVM4 9410 is good use for a medium bin; oem desktop and all-in-one.

I have a med-lo bin a6-9225 (med-lo bin) which performs similar to 9400 (hi bin) but has 15w versus 10w tdp.

I was a bigtime Stoney doubter 2 or 3 years ago, but I think it's proved its worth and paid off even if you account lost sales of Bristol. I think they've pushed this as far as they can though. Dual thread won't last too long anymore. They need to add a pair of threads or retire Stoney next year.
 

DrMrLordX

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@amd6502

Stoney Ridge needs to die. Ryzen mobile has numerous superior CPUs that would do anything better than the best Stoney Ridge ever made, even if you managed to double thread count. With Picasso on the market, AMD would be insane to continue development of Stoney.

Also do not expect any consumer-facing FDX products from AMD. It is unclear that AMD's WSA even covers FDX wafers. I'm pretty sure they've only agreed to take 14/12nm wafers. They are probably not even taking 28nm at this point.
 

NostaSeronx

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@DrMrLordX

Stoney however costs less compared to Raven2(Ryzen 3200u/Athlon 300u). After the A9-9435/A6-9235 SKUs, AMD should move on to the next architecture for the Entry/Low/Mid -end market with Globalfoundries.


With the 22FDX Global HVM ramp(hopefully)... at the high capacity fabs;
Fab 1 => >100k wspm (Bernin 2-Local SOITEC/>800k to 1m)
Fab 7 => >70k wspm (Pasir Ris 1-Local SOITEC/>800k to 1m)
Fab 8 => >60k wspm
Fab 11 => >80k wspm (Local 300mm is Simgui/>800k)
Not explicitly used just for FDX.

Four potential fabs with 22FDX or one fab with only 14LPP(Samsung)/12LP(GloFo modified(more expensive/no protection of second fab)).

The 7th WSA is post-pivot, I would expect 22FDX/12FDX to be preferred.
 
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amd6502

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Stoney Ridge needs to die. Ryzen mobile has numerous superior CPUs that would do anything better than the best Stoney Ridge ever made, even if you managed to double thread count.
You might be right, and that's not even counting the competition from Acorn and other risc socs. I think because of the cheapness (1.1B transistors vs ~2.5B Raven2) and decent gpu they've managed to make it into certain areas like the entertainment displays in passenger aircraft. Stoney is also decent enough for consumer stuff like craptop and chromebook, and with 25W tdp even low to medium bins make a good www+email station.

top bins -> 6w and 10w
med hi -> 10w and 15w
med -> 15w and 25w
lo -> 25w

I think they could add just +25% transistors, get a process upgrade (eg 28fdx or 22fdx) and surf the low end another five years. Otherwise software bloat, as well as competion from mostly cheap quadcore ARM is going to make Stoney/XV fade into history.
 
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DrMrLordX

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I think they could add just +25% transistors, get a process upgrade (eg 28fdx or 22fdx)
Not gonna happen. AMD isn't going to take FDX wafers, nor are they going to spend cash porting XV over to a different node.

and surf the low end another five years.
All AMD has to do is drop clocks on Picasso and it's a done deal. They're already incredibly cheap to make, and they've gotta do something with all that 12nm capacity they're still on the hook to use, so why not? At this point it's just a question of how badly they want to service the low-end market. That market is at near-zero priority with Dr. Su at the helm.
 

NostaSeronx

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nor are they going to spend cash porting XV over to a different node.

All AMD has to do is drop clocks on Picasso and it's a done deal. They're already incredibly cheap to make, and they've gotta do something with all that 12nm capacity they're still on the hook to use, so why not? At this point it's just a question of how badly they want to service the low-end market. That market is at near-zero priority with Dr. Su at the helm.
If AMD sees it is better to go on to 22FDX/12FDX for low-cost/entry/low-mid end APUs. They will do it over salvaging a high-cost/enthusiast/high-end+premium APUs to that same market.

AMD has an existing product that would be easier to make low cost with Stoney. To get Raven2/Picasso towards the same market would require cuts in performance or a new FEOL layer. GlobalFoundries' FinFETs are not all encompassing as TSMC's FinFETs.

A Stoney port to 22FDX => Higher performance, lower power, lower cost, lesser variability.
A Raven2 port to 6W => Lower performance, lower power, higher cost, higher variability.
 
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amd6502

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If AMD sees it is better to go on to 22FDX/12FDX for low-cost/entry/low-mid end APUs. They will do it over salvaging a high-cost/enthusiast/high-end+premium APUs to that same market.

AMD has an existing product that would be easier to make low cost with Stoney. To get Raven2/Picasso towards the same market would require cuts in performance or a new FEOL layer. GlobalFoundries' FinFETs are not all encompassing as TSMC's FinFETs.

A Stoney port to 22FDX => Higher performance, lower power, lower cost, lesser variability.
A Raven2 port to 6W => Lower performance, lower power, higher cost, higher variability.
Only very top bin of Stoney actually performs at 6W, and a good binning is needed to do okay at 10W.

We'll have to wait and wait for reviews to see if Raven2 makes it to 6W. My guess is it should do 10W nicely.

It's half the size of RR, so about half cost. (but still well over twice Stoney's transistor count).
 

NostaSeronx

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However, Stoney is already at 6W. Ryzen 3200u/Athlon 300u aren't at 6W. Then, there is the next node problem.

28BLK -> 22FDX -> 12FDX (Two nodes within GlobalFoundries)
14LPP -> 7FF(Later node outside GlobalFoundries)

28BLK to 22FDX
45% higher frequency (LVT)
45% lower power (RVT)
45% lower area (All VT w/ 8T libs) // ~0.8x smaller than 28BLK/9T die(GF numbers)

22FDX to 12FDX
26% higher frequency (xVT)
47% lower power (xVT)
52% lower area (xVT w/ 7.5T libs) // ~0.77x smaller than 14LPP/9T die(GF numbers)
- xVT is a single VT, probably sLVT.

To get the same increase in performance from 28BLK to 22FDX, Raven2 will need to jump to a SAQP or a EUV node with 7nm. The cost-effective EUV node apparently is the 6nm node. Then 22FDX to 12FDX would need that design to jump to 5nm or 4nm.

The roadmap currently from all the numbers released from the 2H 2018(China-EE industry) and recent post-pivot info.
A9-9435 and A6-9235 => Q4 2019
22FDX APU => Q2 2020 (9 months after the last? Stoney Refresh)
12FDX APU => Q2 2022 (2 years after the 22FDX launches)

The inexpensive option is of course the 28BLK -> 22FDX -> 12FDX path.
The expensive option is then 14LPP(Raven2) -> 7FF(___) -> 4LPP/5FF(___) path.

If AMD wants to be aggressive it will be harder to do with the FinFET APUs. Which the cost of can get in the way of OEMs want of faster/larger RAM, better screens, etc.
 
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