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AMD Bristol/Stoney Ridge Thread

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My suggestion for an AMD AM4 motherboard----> Mini-DTX (re: Mini-DTX will fit in a dual slot Mini-ITX case like the Coolermaster Elite 110, but allow for the M.2 to be on the front of the motherboard (where the M.2 SSD gets airflow) rather than on the back like Intel Mini-ITX LGA 1151 boards.)
 
So, I've been fiddling with BriR/StoR. I have come to some conclusions that need to be tested or verified by others.

1#;
- 28nm Super Low Power, 28nm Advanced, 28nm High Performance Plus are all created with 32nm Geometry.
- 28nm High Performance Advanced however is created with 22nm Geometry. [Which is why we have seen it with 22FDX]

2#;
The architecture used is not "Excavator", but is in fact "Drillcorer" or simply Driller. Other than the inclusion of the Fully Integrated Voltage Regulator.
- I have identified some optimizations to WCC, TLBs, and Vector Processing Unit.
- I have identified some regressions to L1d latency, L2 latency, and an erroneous identification of a 4 MB L3 cache on Bristol Ridge. [44c for L3, 19c for L2, 5c for L1d]

VPU Change;
Pipe 0; FPFMA, FPCVT
Pipe 1; FPFMA, FPXBR
Pipe 2; FPMMA, FPMAL
Pipe 3; FPMAL, FPSTO, FPSHF

WCC only evicts to the L2. Where with Piledriver, it went everywhere. Kaveri retained the same behavior.

Essentially, a fusion of bdver1/2 and bdver3/4. No big boggling changes, everything should performance the same. Except, for workloads that mix Vector FP and Packed Int.
 
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dooon said:
AMD PRO A-Series APU "Desktop Bristol Ridge" vs "Desktop Skylake" Spec
vpvXsEV.png
Click to expand...

How is it that the 2 core has 2MB L2 cache? Wasn't the cache per module in previous construction cores? Would have expected 1MB if the 4 core versions have 2MB.
 
Last edited:
NostaSeronx said:
So, I've been fiddling with BriR/StoR. I have come to some conclusions that need to be tested or verified by others.

1#;
- 28nm Super Low Power, 28nm Advanced, 28nm High Performance Plus are all created with 32nm Geometry.
- 28nm High Performance Advanced however is created with 22nm Geometry. [Which is why we have seen it with 22FDX]

2#;
The architecture used is not "Excavator", but is in fact "Drillcorer" or simply Driller. Other than the inclusion of the Fully Integrated Voltage Regulator.
- I have identified some optimizations to WCC, TLBs, and Vector Processing Unit.
- I have identified some regressions to L1d latency, L2 latency, and an erroneous identification of a 4 MB L3 cache on Bristol Ridge. [44c for L3, 19c for L2, 5c for L1d]

VPU Change;
Pipe 0; FPFMA, FPCVT
Pipe 1; FPFMA, FPXBR
Pipe 2; FPMMA, FPMAL
Pipe 3; FPMAL, FPSTO, FPSHF

WCC only evicts to the L2. Where with Piledriver, it went everywhere. Kaveri retained the same behavior.

Essentially, a fusion of bdver1/2 and bdver3/4. No big boggling changes, everything should performance the same. Except, for workloads that mix Vector FP and Packed Int.
Click to expand...

Could you provide some evidence of how you came to these conclusions?
 
dooon said:
HP Pavilion Desktop 510-p118ns
APU AMD Quad-Core A10-9700 (3,5 GHz, hasta 3,8 GHz, 2 MB de caché)
http://www8.hp.com/h20195/v2/GetPDF.aspx/c05213625.pdf
Click to expand...

That full size mATX tower has a 180W AC adapter just like the following HP Pavilion 510 desktop:

http://store.hp.com/us/en/pdp/hp-pavilion-510st-desktop-pc-v9a74aa-aba-pc (35W Intel i7 + GT730 DDR3):

I wonder how many amps on the 12V rail(s)?

My concern would be there is not sufficient amps to power a dGPU in addition to a 65W APU, which negates one of the advantages of the large form factor.

EDIT: the A10-9700 APU desktop does come with a R5 435 GDDR5 dGPU.

(Ok, well settles that question. At this point though I can only hope these 65W quad core APU desktops with dGPU could be replaced by 65W dCPU + dGPU. Then focus the APUs* into mobile and BGA SFF applications.)

*exception being the harvested dual core APUs.
 
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dooon said:
HP Pavilion Desktop 510-p118ns
APU AMD Quad-Core A10-9700 (3,5 GHz, hasta 3,8 GHz, 2 MB de caché)
http://www8.hp.com/h20195/v2/GetPDF.aspx/c05213625.pdf
Click to expand...

Thanks.

4GB + 8GB RAM combination + discrete graphics. Amazing.

At least looks like there's an M.2 slot, so if this is an indication that it will be available as standard on AM4 MB's that's good.

dooon said:
AMD PRO A-Series APU "Desktop Bristol Ridge" vs "Desktop Skylake" Spec
vpvXsEV.png
Click to expand...

Looking at this again, I really hope this comparison with Intel chips doesn't intend to imply price points.
 
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Wow, there's so much (too much) great information in this thread, but I'm having difficulty establishing what's what. I was thinking of pulling the trigger on a $150 mITX/7860K combo at Microcenter to build a tiny little HTPC (with light gaming), but having HEVC decode in hardware would be amazing for some of the newer files I've been playing with.

When can I buy one of these new AM4 motherboards and Bristol Ridge APUs to get 4K HEVC Main10 60fps and VP9 decode?
 
DT Bristol Ridge schedule was for late july, so it shouldnt be long before MBs and APUs are launched, surely next month or early october, i guess that they are waiting for current DT APUs inventories to be low enough, because once BR is launched Kaveri sales will logicaly plummet...
 
Abwx said:
DT Bristol Ridge schedule was for late july, so it shouldnt be long before MBs and APUs are launched, surely next month or early october, i guess that they are waiting for current DT APUs inventories to be low enough, because once BR is launched Kaveri sales will logicaly plummet...
Click to expand...

No dude, more than a couple of times (esp with AT articles) the author has "hinted" they've noticed lack of desktop AM4 parts and understand AMD are waiting for Zen for a full top-bottom launch.
 
Quite possible but then it doesnt make much sense on a financial POV unless their Kaveri sales in the meantime are good enough, and even in this case a BR + KV offering would bring more revenues.
 
DrMrLordX said:
I thought DIY Bristol Ridge on AM4 was due in Octobor, with OEM Bristol Ridge coming before then?
Click to expand...

I hope you're correct. I side with the speculation that BR was delayed closer to Zen for a few reasons. Launch with lowest performance CPUs would effect public perception of AM4 as a whole. But I also suspect the ecosystem could be confusing when viewed only using BR, e.g. unused SATA or PCIe ports on the motherboard.

I'd assume AMD is spending their time stocking up OEMs (which the OEM likes) before opening up consumer channels. All that being said, October is Q4 and AMD has been saying Q4 is Zen time, perhaps we are all correct and they'll do a BR/SR and AM4 platform launch with more info and limited (zero) supply of Zen.
 
I don't really understand the strategy here. Keep a lid on BR in order to focus comparisons between Kaveri and Zen? I suppose the it makes for more impressive slides to show investors. I'm not in a huge rush to build this mITX machine, but the suspense is killing me.
 
So far as I can tell, Zen isn't being compared to Steamroller (Kaveri). It's being compared to Excavator (Carrizo/Bristol Ridge).

And yeah I figured OEM Bristol Ridge was already available, I just didn't remember where. Thanks for the reminder Abwx.
 
Does anyone know what type of eMMC support Stoney Ridge has? eMMC 5.0 or eMMC 5.1?

Intel has eMMC 4.51 support on Bay Trail (silvermont atom) and Cherry Trail/Braswell (airmont atom). Apollo Lake (Goldmont atom) has eMMC 5.0 support.
 
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