cbn
Lifer
- Mar 27, 2009
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How is it that the 2 core has 2MB L2 cache? Wasn't the cache per module in previous construction cores? Would have expected 1MB if the 4 core versions have 2MB.AMD PRO A-Series APU "Desktop Bristol Ridge" vs "Desktop Skylake" Spec
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Could you provide some evidence of how you came to these conclusions?So, I've been fiddling with BriR/StoR. I have come to some conclusions that need to be tested or verified by others.
1#;
- 28nm Super Low Power, 28nm Advanced, 28nm High Performance Plus are all created with 32nm Geometry.
- 28nm High Performance Advanced however is created with 22nm Geometry. [Which is why we have seen it with 22FDX]
2#;
The architecture used is not "Excavator", but is in fact "Drillcorer" or simply Driller. Other than the inclusion of the Fully Integrated Voltage Regulator.
- I have identified some optimizations to WCC, TLBs, and Vector Processing Unit.
- I have identified some regressions to L1d latency, L2 latency, and an erroneous identification of a 4 MB L3 cache on Bristol Ridge. [44c for L3, 19c for L2, 5c for L1d]
VPU Change;
Pipe 0; FPFMA, FPCVT
Pipe 1; FPFMA, FPXBR
Pipe 2; FPMMA, FPMAL
Pipe 3; FPMAL, FPSTO, FPSHF
WCC only evicts to the L2. Where with Piledriver, it went everywhere. Kaveri retained the same behavior.
Essentially, a fusion of bdver1/2 and bdver3/4. No big boggling changes, everything should performance the same. Except, for workloads that mix Vector FP and Packed Int.
That full size mATX tower has a 180W AC adapter just like the following HP Pavilion 510 desktop:HP Pavilion Desktop 510-p118ns
APU AMD Quad-Core A10-9700 (3,5 GHz, hasta 3,8 GHz, 2 MB de caché)
http://www8.hp.com/h20195/v2/GetPDF.aspx/c05213625.pdf
Thanks.HP Pavilion Desktop 510-p118ns
APU AMD Quad-Core A10-9700 (3,5 GHz, hasta 3,8 GHz, 2 MB de caché)
http://www8.hp.com/h20195/v2/GetPDF.aspx/c05213625.pdf
Looking at this again, I really hope this comparison with Intel chips doesn't intend to imply price points.AMD PRO A-Series APU "Desktop Bristol Ridge" vs "Desktop Skylake" Spec
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No dude, more than a couple of times (esp with AT articles) the author has "hinted" they've noticed lack of desktop AM4 parts and understand AMD are waiting for Zen for a full top-bottom launch.DT Bristol Ridge schedule was for late july, so it shouldnt be long before MBs and APUs are launched, surely next month or early october, i guess that they are waiting for current DT APUs inventories to be low enough, because once BR is launched Kaveri sales will logicaly plummet...
I hope you're correct. I side with the speculation that BR was delayed closer to Zen for a few reasons. Launch with lowest performance CPUs would effect public perception of AM4 as a whole. But I also suspect the ecosystem could be confusing when viewed only using BR, e.g. unused SATA or PCIe ports on the motherboard.I thought DIY Bristol Ridge on AM4 was due in Octobor, with OEM Bristol Ridge coming before then?
It s already on sale, and hence also AM4 MBs, but only on HP s DTs, so far HP has a 2 months exclusivity on the mobile variant but looks that extend to DT SKUs as well, link below was provided by Dooon a feww post before this one.I thought DIY Bristol Ridge on AM4 was due in Octobor, with OEM Bristol Ridge coming before then?
Between Nehalem/SB levels? interesting....FP results in old SUperpi with Carizzo:
http://hwbot.org/newsflash/3882_newlife_hits_sub_10min_superpi_32m_score_on_amd_athlon_x4_845._is_amds_28nm_process_improving
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