AMD “Next Horizon Event" Thread

[TimCh]

so the predictions on memory latency (and thus the gaming performance) ? how come that AMD claims better latency with de-integrated memory controller ? the L4 (/wave Broadwell) ?

Compared with Epyc(1) it should be pretty easy to improve latency, with the current Epyc 75% of the memory channels are remote with really high latency (around 130-150 ns depending on the memory). Infinity Fabric 2 has a lot of improvements to latency.

 

[coercitiv]

Same 8C chiplet. Right down to the basement.

What basement? I was replying to a post talking about 8c being the minimum core count in Zen 3000 series.

 

[Abwx]

Since those CPUs are for servers, the first thing we are interested to know is how much power each system used to finish the C-Ray benchmark and secondly, how much space each system will use because rack space is gold in server rooms.

The interesting comparison is with Epyc 7601, either they were clocked at same speed and the improvement is 8.5%, or the Epyc 2 was clocked lower than the 7601s 2.2GHz base.

So far the only speculative leak about ESs frequencies is the ChipHell one with a chip allegedly running at 1.8GHz, AMD could have used something clocked at say 2GHz to not disclose the exact perf improvement, C-Ray scale very well but here it wasnt even needed since this is 64C vs 64C.

So if EPYC 2 is 10% faster than dual XEONs but using 30-40% less power and can fit the same amount of cores at half the rack space then we are talking about a major advantage for the AMD product vs the competition.

30% lower power in FP is already the case with Epyc 32C vs Xeon 28C, even with its forcibly more power hungry FPU (at same node) Epyc 2 should still be at 0.4x the power at same FP perfs than the Xeon.

https://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd-epyc-7000-cpu-battle-of-the-decade/22

 

[amd6502]

4.8 GHz alone would be amazing even for boost. You have a big FPU upgrade and we expect decent IPC increase.

 

[Atari2600]

What basement? I was replying to a post talking about 8c being the minimum core count in Zen 3000 series.

Ryzen3.

I can see the path of least resistance for AMD being to use the 8C chiplet from top to bottom in the product stack, no exceptions.

It'd likely be more cost effective for them to deactivate cores than do a 4C custom design. [edit: meant cores, not dies]

 

[jpiniero]

Same 8C chiplet. Right down to the basement. They might not even offer a 4 core Zen2 product (unless harvesting duds I guess).

Yeah that would be the reason. 7 nm yields are likely bad. Not Intel bad of course but the Ryzens are going to be needed to soak up the 4 and 6 core possible dies while Epyc gets the full dies.

If Zen 2 allows for mismatched core counts per die/CCX that would make things more flexible.

 

[coercitiv]

Ryzen3.

I can see the path of least resistance for AMD being to use the 8C chiplet from top to bottom in the product stack, no exceptions.

I feel like we're speaking past each other. I expressed concern over the idea that Ryzen 3000 would end up using multiple 7nm chiplets togheter with an arguably sizeable IO die in the mainstream consumer line. That concern was directly related to manufacturing cost. You keep talking about design cost.

Whether Ryzen 3000 series should or would use a custom design is another discussion altogether, my issue is with the idea of Ryzen 3000 starting at 8c/8t minimum and building towards 16c/32t in order for segmentation to allow multiple price points, including that sweet sub $200 spot. It would be expensive and it would also have problems scaling with dual channel memory.

 

[maddie]

Yeah that would be the reason. 7 nm yields are likely bad. Not Intel bad of course but the Ryzens are going to be needed to soak up the 4 and 6 core possible dies while Epyc gets the full dies.

If Zen 2 allows for mismatched core counts per die/CCX that would make things more flexible.

Apple (A12 = 83mm^2) and Huawei (Kirin 980 = 75mm^2) are both around the same size as the Zen2 chiplet, and AFAIK, there's no die harvesting of those SOCs. Why would think yields are so terrible for a die that size?

 

[PeterScott]

I feel like we're speaking past each other. I expressed concern over the idea that Ryzen 3000 would end up using multiple 7nm chiplets togheter with an arguably sizeable IO die in the mainstream consumer line. That concern was directly related to manufacturing cost. You keep talking about design cost.

Whether Ryzen 3000 series should or would use a custom design is another discussion altogether, my issue is with the idea of Ryzen 3000 starting at 8c/8t minimum and building towards 16c/32t in order for segmentation to allow multiple price points, including that sweet sub $200 spot. It would be expensive and it would also have problems scaling with dual channel memory.

Remember Ryzen 1000 series. One 8 core chip providing 4 core, 6 core and 8 core products.

Regardless whether it is chiplet or monolithic, I don't see why there would be an issue doing that again.

Also why do you think there must be 16 cores on the mainstream desktop?

 

[jpiniero]

Apple (A12 = 83mm^2) and Huawei (Kirin 980 = 75mm^2) are both around the same size as the Zen2 chiplet, and AFAIK, there's no die harvesting of those SOCs. Why would think yields are so terrible for a die that size?

Huawei I don't know about I do imagine Apple will repurpose the defective dies for future products.

Also have to factor in that they are doing substantially higher volume than AMD could ever dream about, so they are getting a much better deal in terms of wafer costs.

 

[coercitiv]

Also why do you think there must be 16 cores on the mainstream desktop?

If 8c/8t is R3, where is R7?

 

[Atari2600]

I feel like we're speaking past each other. I expressed concern over the idea that Ryzen 3000 would end up using multiple 7nm chiplets togheter with an arguably sizeable IO die in the mainstream consumer line. That concern was directly related to manufacturing cost. You keep talking about design cost.

Whether Ryzen 3000 series should or would use a custom design is another discussion altogether, my issue is with the idea of Ryzen 3000 starting at 8c/8t minimum and building towards 16c/32t in order for segmentation to allow multiple price points, including that sweet sub $200 spot. It would be expensive and it would also have problems scaling with dual channel memory.

Ah, right, gotcha now.

Nah, can't see it starting at 8C minimum - unless they've a lot of leakage variance allowing them to segment the market by bins (clock speed).

They'd likely harvest bad dies to form 4C and 6C offerings.

Re. a 16C AM4 version - I had thought about this - and thought it'd be a bad idea, I actually had a post written saying as much - then realised that it would actually have better memory access than the 2990WX per core, clue much editing of my post. 2990WX works very well for rendering, so I don't really see a technical reason why a 16C on AM4 wouldn't sell well - if clockspeeds and power consumption make sense.

 

[coercitiv]

Re. a 16C AM4 version - I had thought about this - and thought it'd be a bad idea, I actually had a post written saying as much - then realised that it would actually have better memory access than the 2990WX per core, clue much editing of my post. 2990WX works very well for rendering, so I don't really see a technical reason why a 16C on AM4 wouldn't sell well - if clockspeeds and power consumption make sense.

We'll see I guess. Beside price, which we can argue it's still ultimately flexible as long as there's proper value at $200 and $300 price points, there's one more thing though: whatever Ryzen 3000 can do at 16c/32t, Threadripper will do much better.

My bet is this gen will focus on maximizing 8c/16t performance on AM4. I'm not 100% convinced about this, maybe 12c/24t makes sense still, maybe I'm missing an important part of the picture considering this is just an entertaining hobby for me (no professional background, just enough engineering education to understand the basics), but I would rather entertain the idea of Ryzen 3000 being all APUs rather than Threadrippers with bandwidth issues.

One thing is for certain though, I think I may have to buy one.

 

[jpiniero]

I was going to suggest something like this:

R9 12C24T
R7 8C16T or 10C20T (if allowed, and either would be 2 dies)
R5 6C12T (could do a model with 2 dies and more L3, and another with one die)
R3 4C8T and 4C4T (one die)

 

[zrav]

My bet is this gen will focus on maximizing 8c/16t performance on AM4. I'm not 100% convinced about this, maybe 12c/24t makes sense still

I don't think it makes much sense to offer >8c on dual channel memory. It would also mean added design cost for yet another CPU configuration (and possibly another IO die), apart from eating into TR's market segment.

 

[DrMrLordX]

I don't think it makes much sense to offer >8c on dual channel memory. It would also mean added design cost for yet another CPU configuration (and possibly another IO die), apart from eating into TR's market segment.

16c could work though, even bandwidth-starved. Also the next Threadripper spin may have 16c as its low-end point. We are going to see 64c Threadripper in 2019, mark my words . . .

 

[IntelUser2000]

I don't think it makes much sense to offer >8c on dual channel memory.

Sure it can. Especially if we are moving 4 cores into value $500 range systems and 8 cores into mainstream. You'll end up with people surfing the internet and watching videos buy 8 core systems. Memory bandwidth is no issue.

Core wars are just like regular wars that its illogical. You do it because you are forced to. Competition, lack of progress in process tech, and general desire that newer products be made to be sold makes it happen.

 

[mattiasnyc]

Is it out the question for AMD to continue the current gen Ryzen dies and designs for the lower end and just have GloFo improve the process or something? I'm just sort of thinking that the design already exists, the process exists, and it seems it'd be easy to just keep producing those parts for the lower end. That in a sense gets rid of the "problem" of 'starting' with an 8-core part at the low end (assuming that problem exists in the first place).

 

[Abwx]

Huawei I don't know about I do imagine Apple will repurpose the defective dies for future products.

Also have to factor in that they are doing substantially higher volume than AMD could ever dream about, so they are getting a much better deal in terms of wafer costs.

That s not the same market, those 8 chiplets + 4cm2 I/O compete more than favourably against a dual Xeon 28C MCM that is sold 13k$ or so, if they sell their chip 7k$ they would still make very good margins.

Competitively speaking the 56C Xeon MCM is rated 1.8GHz@300W while a Epyc 2 64C should be within the same 2GHz@180W as a 32C Epyc 1, at 2x the perf/watt and much lower CPU cost whoever go the Intel route in 2019 will sure help his company go the the dodo s way of life...

 

[PeterScott]

If 8c/8t is R3, where is R7?

You didn't read the lines before that:

One 8 core chip providing 4 core, 6 core and 8 core products.

R3 = 4c
R5 = 6c
R7 = 8c

Same as today.

 

[jpiniero]

That s not the same market, those 8 chiplets + 4cm2 I/O compete more than favourably against a dual Xeon 28C MCM that is sold 13k$ or so, if they sell their chip 7k$ they would still make very good margins.

That's Epyc, not Ryzen.

 

[Atari2600]

We'll see I guess. Beside price, which we can argue it's still ultimately flexible as long as there's proper value at $200 and $300 price points, there's one more thing though: whatever Ryzen 3000 can do at 16c/32t, Threadripper will do much better.

My bet is this gen will focus on maximizing 8c/16t performance on AM4. I'm not 100% convinced about this, maybe 12c/24t makes sense still, maybe I'm missing an important part of the picture considering this is just an entertaining hobby for me (no professional background, just enough engineering education to understand the basics), but I would rather entertain the idea of Ryzen 3000 being all APUs rather than Threadrippers with bandwidth issues.

One thing is for certain though, I think I may have to buy one.

I suspect AMD are going to have 2 IO Controllers (IOC).

The one we already know about - Rome - with 8 Infinity Fabric (IF) ports so they can run 8x8C chiplet = 64 cores. All EPYC and TR variants will used fused down versions of this IMO - both in terms of fusing off IF ports and in dropping memory channels.


Then the other IOC is a much smaller 2x IF port version with dual channel memory controller, for use in:
(i) APU - 1x8C* chiplet + 7nm Vega (AMD already have announced 7Vega can communicate via IF).
(ii) Mainstream with 1 of the ports fused off, so 1x8C* chiplet.
(iii) High end of mainstream for 2x8C* chiplets.

*CPU cores fused off as required by market/salvage.


So 1x 7nm chiplet design and 2x 14nm IOC designs to cover the market from 4C APU right through to 64C Rome. Pretty efficient use of resources IMO.

 

[Abwx]

That's Epyc, not Ryzen.

They can extract 850 chiplets/waffer, yields are likely good given the low surface but even at 70% and 15k$/waffer the die cost wouldnt exceed 17$, a complementary I/O 12nm chip for say a 8C or 16C DT part would be something like 80mm2 at 10$.

 

[coercitiv]

You didn't read the lines before that:

And you weren't following the discussion I was having at all, so why intervene if not on topic?

 

[PeterScott]

And you weren't following the discussion I was having at all, so why intervene if not on topic?

I followed that you were making a ridiculous assumption that R3 would be 8cores, when it most cerainly will not be.