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AMD “Next Horizon Event" Thread

csbin

Senior member
Feb 4, 2013
813
0
136
#1
7nm Zen2,EPYC 2,7nm Vega20,Navi,one more thing?;)
 

cortexa99

Junior Member
Jul 2, 2018
20
2
41
#2
What I heard about Zen2:

1. IPC higher than expected
2. memory latency is mainly improvement
3. AVX performance improve(still no AVX-512)
4. 7nm frequency preview
5. much precise turbo boost
 
Jan 28, 2017
58
0
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#3
There's a lot of big dreams about Rome, but really, it Zen 2 comes just meeting AMD expectations, isn't enough?
+10% IPC, -10ns latency, +300-400MHz base and top frequency, "improved" FPU.
Just this isn't enough?
10 months after comes the new refresh with +100MHz and -5ns latency.
Better drivers, better BIOS, enough to stay competitive, right?
 
Mar 10, 2004
27,788
45
126
#4
I want AMD to do better than that because I think Intel needs a big kick in the butt right about now.
 

Hitman928

Golden Member
Apr 15, 2012
1,548
6
136
#5
Anyone know what time the event starts?
 
Mar 10, 2004
27,788
45
126
#6
Noon on the east coast.
 

thecoolnessrune

Diamond Member
Jun 8, 2005
9,260
13
126
#9
It's cheap, but part of me hopes that AMD comments about the "cheap glue" Intel is using to bond Cascade-Lake AP together. :D
 
Nov 6, 2014
110
4
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#10
Is there going to be any stream/blog or is this a closed event?

Edit: stupid of me, there is even at Anandtech.
 

coercitiv

Platinum Member
Jan 24, 2014
2,906
106
136
#13
Modular System Design
 

Topweasel

Diamond Member
Oct 19, 2000
4,500
94
126
#16
Awsome. AVX-2 Native support.
 

The Stilt

Golden Member
Dec 5, 2015
1,700
18
106
#17
A wide(r) core, finally :)
 

Hitman928

Golden Member
Apr 15, 2012
1,548
6
136
#18
Chiplet design confirmed.

IO chip is 14 nm.
 

Topweasel

Diamond Member
Oct 19, 2000
4,500
94
126
#21
Chiplet confirmed, confirmed.
 

beginner99

Diamond Member
Jun 2, 2009
3,879
24
126
#22
Chiplets and 14nm IO die are real. That is the big take-away for Zen 2.

256-bit floating point, higher IPC. Else not much info on clocks or actual performance.
 

Tuna-Fish

Senior member
Mar 4, 2011
902
27
116
#23
The next big question I have is how much cache does that IO die have? To host all that IO, it needs a large circumference. So a lot would fit, even at 14nm.
 
Nov 6, 2014
110
4
101
#24
13,2b transistors @ 331mm2 for vega 7nm.
 

beginner99

Diamond Member
Jun 2, 2009
3,879
24
126
#25
1 TB/s memory bandwidth for Mi60.

pcie 4.0!
 

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