"7 Watt" Ivy Bridge my arse!

[AtenRa]

Does anyone have any benchmarks of an ivy bridge i5 capped at 800MHz? I'm sure an i5 clocked at 800Mhz would still slaughter an atom or an E-450 but I would like to know by how much.

I will give you 100%(2x) more IPC for the IvyBridge Core over Bobcat. Now, E-450 is at 1.7GHz, that is 2x higher frequency. I will say they will have almost the same performance.

Now add 15+% more IPC for the Jaguar and >10% more frequency at the same power budget and it seams to me that IvyBridge at 800MHz will loose big time.

 

[Nemesis 1]

Well we shall all get to see , All I see is more disappointment and outrage of AMD fanbois. Silvermont will likely beat up on Temash . Comparring to IVB/haswell is going no where

 

[Nemesis 1]

I can't believe that worked out so perfectly.

Anada all ready covered it in the Tablet comparison , Its a good read and its what has the AMD army up and fighting another losing battle

 

[Exophase]

I can't believe that worked out so perfectly.

That's because he selected the voltage specifically to fit the curve, to show that it was possible. We don't actually know what kind of voltage reduction the temperature shift alone will allow.

I'm personally not at all saying it's impossible, but I'm glad to see IDC concur with the rest of us - we don't know. Intel's marketing is still ambiguous on this and I think it's justifiable to be uncomfortable with this.

One other note - shouldn't it be 10W to 7W, not 13W to 7W? Aren't you starting with cTDPdown, not TDP?

 

[sm625]

I will give you 100%(2x) more IPC for the IvyBridge Core over Bobcat. Now, E-450 is at 1.7GHz, that is 2x higher frequency. I will say they will have almost the same performance.

Now add 15+% more IPC for the Jaguar and >10% more frequency at the same power budget and it seams to me that IvyBridge at 800MHz will loose big time.

Yeah but look at these:

This is sandy bridge celeron 857, 2 cores 2 threads at 1.2GHz. Which is probably equal to ib at 1.1GHz. So ib at 800MHz will get roughly 75% of the celeron 857 scores for a 2core 2thread part. That still puts it way way ahead of the E-450. And this is just a celeron. A full blown i5 with 4 threads and even a minor turbo could come very close to hitting these i3-2330M scores. In fact I am predicting that this 7W ib will score over 5000 in cinebench R10. E-450 only scores 2000.

 

[Idontcare]

That's because he selected the voltage specifically to fit the curve, to show that it was possible. We don't actually know what kind of voltage reduction the temperature shift alone will allow.

I'm personally not at all saying it's impossible, but I'm glad to see IDC concur with the rest of us - we don't know. Intel's marketing is still ambiguous on this and I think it's justifiable to be uncomfortable with this.

One other note - shouldn't it be 10W to 7W, not 13W to 7W? Aren't you starting with cTDPdown, not TDP?

The voltages are not unreasonable though based on what we do know about this process tech and this microarchitecture.

For my 3770k, clocked at 1.6GHz it needs 0.833 volts (measured) to be LinX stable when Tjunction is 105C (pre-throttling, verified).

Drop the loaded temperature from 105C to 36C and the voltage can be reduced from 0.833V to 0.636V.

I didn't bother to see what Vmin would be at 80C, but obviously it is going to be considerably closer to 0.636V than 0.833V owing to the exponential nature of the very S/N issue that gives rise to the need for elevated voltages at elevated operating temperatures in the first place.

 

[piesquared]

I'm wondering what the difference between this new measuring technique, and say an SoC using 1 Watt with fixed function hardware for typical application use. Should the industry now rate chips at 1 Watt if that is a typical usage scenario?

[edit]

Well ok there is a difference but the point remains the same. If I use an application that targets a fixed function block dissipating only 1 W, it could be classified as a 1/3/5/6 whatever Watt chip.

 

[Exophase]

The voltages are not unreasonable though based on what we do know about this process tech and this microarchitecture.

For my 3770k, clocked at 1.6GHz it needs 0.833 volts (measured) to be LinX stable when Tjunction is 105C (pre-throttling, verified).

Drop the loaded temperature from 105C to 36C and the voltage can be reduced from 0.833V to 0.636V.

I didn't bother to see what Vmin would be at 80C, but obviously it is going to be considerably closer to 0.636V than 0.833V owing to the exponential nature of the very S/N issue that gives rise to the need for elevated voltages at elevated operating temperatures in the first place.

Was going to ask if the 36C was at Tj and not ambient, you saved me the trouble I take it this was with some pretty serious cooling. Do you still have this test setup and is it something you could test with to find out? The temperature sensitivity may be exponential but two points alone doesn't say where you are on the curve.

Also, you're now referring to the measured voltage as Vmin rather than just Vcore/Vcc for the device; could you elaborate on the difference?

 

[Piroko]

Just had to register to take part in this discussion...

It is not impossible nor implausible that a processor at 105C uses 13W but at 80C it would use 7W, just means you have a rather leaky process tech at high temperatures and it is also sharply temperature dependent.

While your example is valid, you do make assumptions there. One being that the processor can adjust its voltage as a function of temperature. If you don't adjust voltage, the power difference resembles that which you measured up to 3.1 Ghz in your own testing.
Additionally, I would expect the ulv chips to be binned for low static leakage which would reduce the effect you noticed.

Thus I personally conclude that it's not impossible but in this case highly unlikely to get major power savings with lower temperature.
Also, in a passively cooled ultrabook (or one with a very weak/slow fan) you couldn't let it get to 105° in the first place, that would result in case temperatures of >50°C...

 

[Idontcare]

Was going to ask if the 36C was at Tj and not ambient, you saved me the trouble I take it this was with some pretty serious cooling. Do you still have this test setup and is it something you could test with to find out?

Actually the challenge was not getting it to run at 36C, the challenge is getting it to heat up enough such that the Tj was actually 105C.

36C was with your bog-standard NH-D14. It was only clocked to 1.6GHz after all.

But to get to 105C I had to turn off the fans (passive cooling) and that still wasn't good enough as it would only heat up to ~55C peak. So then I swaddled the NH-D14 with towels (as in linens, wash clothes and the like) to trap the heat...only that still wasn't good enough as it would get to about 80C and no higher.

So eventually what I did to get to 105C was turn off the fans, insulate the NH-D14 with towels, and then put a box over the top of all that to further thermally insulate the CPU.

Only then would it get to 105C provided I left it running LinX for nearly 3 hrs

The temperature sensitivity may be exponential but two points alone doesn't say where you are on the curve.

Even if the curvature of the exponential was essentially flat (a linear line between the two points) the expected Vmin for 80C would be 0.765V. It would most assuredly be less than this value, but it would definitely not be higher than this value.

That means the Vmin goes from 0.833V at 105C to 0.765V at 80C, a reduction of 0.0678V.

Going back to your specific assertion that the reduction from 10W to 7W could not be ascribed solely to the reduction in temperature:

At 1.4GHz, 105C, and 0.670V the power use would be 10.02W
At 1.4GHz, 80C, and 0.615V the power use would be 7.04W

The voltage delta is a mere 0.055V, less than the worst-case voltage delta we can envision observing for my 1.6GHz (higher clocked even) 3770k in going from 105C to 80C.

Also, you're now referring to the measured voltage as Vmin rather than just Vcore/Vcc for the device; could you elaborate on the difference?

I define Vmin as the minimum voltage necessary for the system to be stable enough to handle at least 5 cycles of LinX (~3hrs at these clocks) with problem size 43122 (~14.2GB).

Vcc/Vcore are the same thing, but you can set Vcore/Vcc to any value greater than or equal to Vmin and still run stable.

You are basically asking what is the difference between Tj and Tjmax. At TJmax they are both the same, Tj=TJmax when Tj is at Tjmax

Vcc/Vcore = Vmin when you set Vcc/Vcore to be equal to Vmin But you don't have to set them to be equal, you just don't want to set Vcc/Vcore < Vmin (because then your rig crashes).

 

[Nemesis 1]

I'm wondering what the difference between this new measuring technique, and say an SoC using 1 Watt with fixed function hardware for typical application use. Should the industry now rate chips at 1 Watt if that is a typical usage scenario?

[edit]

Well ok there is a difference but the point remains the same. If I use an application that targets a fixed function block dissipating only 1 W, it could be classified as a 1/3/5/6 whatever Watt chip.

This really wasn't the place to discuss this topic. But it is interesting none the less.

 

[Exophase]

Going back to your specific assertion that the reduction from 10W to 7W could not be ascribed solely to the reduction in temperature

Please, enough. I never asserted this!

I asked several times IF it's entirely due to the reduction in temperature or not. Asked. Not asserted one way or the other. Is it really that hard to tell the difference?

I think that your data certainly provides enough plausibility for this to be the case.

 

[Idontcare]

Welcome to the forums Piroko :thumbsup:

Thus I personally conclude that it's not impossible but in this case highly unlikely to get major power savings with lower temperature.

If that were true then why would Intel bother incorporating a reduction in max allowed operating temperature into the SDP spec in the first place?

Obviously the engineers who made the spec are expecting temperature to play a considerable role in the processor's power footprint, otherwise they would have left the power spec in place with the existing TJmax spec.

Also, in a passively cooled ultrabook (or one with a very weak/slow fan) you couldn't let it get to 105° in the first place, that would result in case temperatures of >50°C...

Again, if this were relevant then Intel would not bother to peg their TDP and SDP spec values to 105C and 80C respectively. Clearly they are expecting Tjunction to reach (and exceed) 80C such that they felt it necessary to split the spec to define power usage below 80C versus above 80C.

 

[Idontcare]

Please, enough. I never asserted this!

I asked several times IF it's entirely due to the reduction in temperature or not. Asked. Not asserted one way or the other. Is it really that hard to tell the difference?

I think that your data certainly provides enough plausibility for this to be the case.

Sorry my bad. I had conflated your post here with that of Lepton87's earlier post.

But we are saying the same thing, I too do not think the entire reduction in power usage will be attributed to lower voltage and/or lower leakage from lower temperatures (although obviously some of that will be in play)...I think they are going to deturbo below the base clockspeed in order to fit within the SDP spec because that is exactly what they do now if you hit the TDP spec or TJmax (throttles the clockspeed).

 

[Nemesis 1]

OK. Lets go back in time. what was it intel said about 22nm transitors. You get x performance boost at y voltage. Ring any bells or lower performance at lesser voltage better efficiency. now this mau apply only to high voltage somehow i doubt that . these ivb seem to be borderline. ME myself I would like to see medfield on 22nm To actually see if 36% performance boost is there.

 

[Nemesis 1]

That's because he selected the voltage specifically to fit the curve, to show that it was possible. We don't actually know what kind of voltage reduction the temperature shift alone will allow.

I'm personally not at all saying it's impossible, but I'm glad to see IDC concur with the rest of us - we don't know. Intel's marketing is still ambiguous on this and I think it's justifiable to be uncomfortable with this.

One other note - shouldn't it be 10W to 7W, not 13W to 7W? Aren't you starting with cTDPdown, not TDP?

You need to go back reread he didn't just pick that voltage . There is a reason he choose that voltage . Go back look to see if I am not correct .He even states it .Its more than just the haswell demo runing at 8 watts . There is an underlying reason that set Ananda off.

 

[Exophase]

You need to go back reread he didn't just pick that voltage . There is a reason he choose that voltage . Go back look to see if I am not correct .He even states it .

So I guess when he said he picked the voltage to make the numbers work out he didn't really mean it then?

Now this is just an example, obviously the operating voltages are picked such that the numbers work out but the voltages are also not unreasonable (my 3770k is LinX stable at 1.6GHz with just 0.636V at 36C).

The point is that he plugged in the power consumption to find out what voltages you would need and find they looked reasonable. He didn't plug in voltages he knew to be real world values then just happened to arrive at exactly the power consumption we were talking about. But Blandge's comment about how perfectly it worked out sure makes it sound like that's what he thought happened...

 

[Nemesis 1]

So I guess when he said he picked the voltage to make the numbers work out he didn't really mean it then?



The point is that he plugged in the power consumption to find out what voltages you would need and find they looked reasonable. He didn't plug in voltages he knew to be real world values then just happened to arrive at exactly the power consumption we were talking about. But Blandge's comment about how perfectly it worked out sure makes it sound like that's what he thought happened...

I new you wouldn't come back with the answer even tho you likely know . Frankly I don't care enough to point it out to you . Ananda , Wrote that because of something occurring during his test . Than and only than did it dawn on him what was happening here .Ananda says exactly why he choose 8 watts. Says it plainly

 

[Exophase]

As usual I have no idea what you're talking about. I especially don't understand why you seem to misspell Anand on purpose...

 

[Nemesis 1]

I miss spell all the time i use wrong case all the time, There their no know . speling spelling . is it a big deal to you . Its a big deal to me when a person reads a thing and than doesn't know what they read . like me in core size topic . I didn't see they were discussing the cores until way late , I hate that crap.


Why do you have a reading comprehension problem if you read the article its perfectly clear why he wrote what he wrote

 

[Exophase]

Sorry, I just assumed someone who consistently spells Anand as "Ananda" or "Anada" is doing it on purpose. My mistake.

I can't answer why I have reading comprehension problem because apparently I'm not comprehending what it is I'm not comprehending. Kind of a catch 22. In particular I have no idea why you're talking to me about things Anand wrote because I explained IDC used fixed power numbers to arrive at some voltages instead of the other way around...

 

[Lepton87]

just means you have a rather leaky process tech at high temperatures and it is also sharply temperature dependent.

Does that statement characterize Intel's 22nm process well?

 

[Idontcare]

Does that statement characterize Intel's 22nm process well?

Yes it does.

At 105C more than half of the power dissipation for my 3770k is due to static leakage when clocked at 1.6GHz and 0.833V while running LinX. (16.7W static versus 16.6W dynamic, 33.3W total)

At high temperatures and low voltages (specifically) it is worse than Intel's 32nm process (blue vs green lines in the graph).

 

[Nemesis 1]

Sorry, I just assumed someone who consistently spells Anand as "Ananda" or "Anada" is doing it on purpose. My mistake.

I can't answer why I have reading comprehension problem because apparently I'm not comprehending what it is I'm not comprehending. Kind of a catch 22. In particular I have no idea why you're talking to me about things Anand wrote because I explained IDC used fixed power numbers to arrive at some voltages instead of the other way around...

The spelling thing was fine . I use to it. But it has gotten worse because my keyboard is really touchy. Heres what set Anand off .

In the first section (yellow), we begin playing Modern Combat 3 - a GPU intensive first person shooter. GPU power consumption is just shy of 4W, while CPU power consumption remains below 1W. After about a minute of play we switch away from MC3 and you can see both CPU and GPU power consumption drop considerably. In the next section (orange), we fire up a multithreaded instance of CoreMark - a small CPU benchmark - and allow it to loop indefinitely. CPU power draw peaks at just over 4W, while GPU power consumption is understandably very low.

Next, while CoreMark is still running on both cores, we switch back to Modern Combat 3 (pink section of the graph). GPU voltage ramps way up, power consumption is around 4W, but note what happens to CPU power consumption. The CPU cores step down to a much lower voltage/frequency for the background task (~800MHz from 1.7GHz). Total SoC TDP jumps above 4W but the power controller quickly responds by reducing CPU voltage/frequency in order to keep things under control at ~4W. To confirm that CoreMark is still running, we then switch back to the benchmark (blue segment) and you see CPU performance ramps up as GPU performance winds down. Finally we switch back to MC3, combined CPU + GPU power is around 8W for a short period of time before the CPU is throttled.

Now this is a fairy contrived scenario, but it's necessary to understand the behavior of the Exynos 5250. The SoC is allowed to reach 8W, making that its max TDP by conventional definitions, but seems to strive for around 4W as its typical power under load. Why are these two numbers important? With Haswell, Intel has demonstrated interest (and ability) to deliver a part with an 8W TDP. In practice, Intel would need to deliver about half that to really fit into a device like the Nexus 10 but all of the sudden it seems a lot more feasible. Samsung hits 4W by throttling its CPU cores when both the CPU and GPU subsystems are being taxed, I wonder what an 8W Haswell would look like in a similar situation...

 

[Exophase]

I still don't see what any of that has to do with my pointing out that IDC picked the power numbers to derive the voltages and not the other way around.