Info 64MB V-Cache on 5XXX Zen3 Average +15% in Games

[Kedas]

Well we know now how they will bridge the long wait to Zen4 on AM5 Q4 2022.
Production start for V-cache is end this year so too early for Zen4 so this is certainly coming to AM4.
+15% Lisa said is "like an entire architectural generation"

 

[Joe NYC]

they could cost a lot more they could cost a little more they could cost the same.... who knows , but also consider that azure a deploying them on mass for a reason and its not gaming........

The tasks highlighted by Microsoft in Milan X benchmarks were mostly professional apps that can run either on workstations of servers. Or cloud, as Microsoft is selling it.

On the client side, I don't think the spectrum of applications that would benefit nearly as much is broad enough to put specific marketing emphasis on - outside of gaming. And Gaming (which is broad enough) is where AMD is correctly putting the emphasis for Zen 3D.

But with Microsoft gobbling the supply of Zen 3D dies, who knows when it ends up on the market at MSRP prices....

 

[jamescox]

I was looking at that earlier. That's an odd configuration. If it was 32 cores, AMD could supply it with 4 chiplets, but to supply 36, AMD would need an odd number of chiplets (5?) or give Facebook full 8 chiplets...

Maybe it was a sly move by Facebook to get a CPU with full 256MB of L3 while paying for only 4.5 chiplets... Either way, AMD got its foot in the door, and (what must be embarrassing for Intel), it is one for one replacement of taking out Intel mobo and putting in AMD mobo...

It has only 6 channel memory rather than 8. The Epyc IO die is split into 4 quadrants internally with each one being roughly equivalent to one of the desktop IO die (2 cpu links, 2 x16 pci-e, 2 memory channels). They had 2, 4, 6, and 8 chiplet versions of Rome. Milan has been only 4 or 8 chiplets so far; other configurations are asymmetric. This device appears to just have one quadrant of the IO die disabled, so 6 chiplets (192 MB L3) and 6 channel memory. The 6 active cores per chiplet is likely to fit in the power envelope.

 

[jamescox]

Here is how it works. A potential customer for new or upgrade asked his knowledgeable friend: "Who makes the best CPUs for gaming these days?"
Friend: "Intel"

Goes to the store and asks: "Can I have Intel CPU for about $350"?
Store: "Sure, here is Rocket Lake for you"
Customer: "Thank you for selling me the best CPU"

Or the new processor generation was released and the old generation parts are on sale cheaper?

 

[Markfw]

Or the new processor generation was released and the old generation parts are on sale cheaper?

Don't start this again. Stay on topic "AMD new vcache CPUS". Otherwise I have to have esquared take action again, and you won't like it.

Edit: quoteing @Joe NYC when it talks about Intel to be specific.

 

[Leeea]

Super excited about these.

Hoping to pick up one used 2-3 years from now. Hard to justify over what I have now ( 5900x ), but should be a nice cheap late life upgrade.

 

[eek2121]

Don't start this again. Stay on topic "AMD new vcache CPUS". Otherwise I have to have esquared take action again, and you won't like it.

Edit: quoteing @Joe NYC when it talks about Intel to be specific.

This is reason #262 why I love Mark. 😘 Not because he is a mod (I do try to ignore that flair, even though it gets me banned basically always, but because, for better or for worse, he is a straight shooter.)

 

[Joe NYC]

It has only 6 channel memory rather than 8. The Epyc IO die is split into 4 quadrants internally with each one being roughly equivalent to one of the desktop IO die (2 cpu links, 2 x16 pci-e, 2 memory channels). They had 2, 4, 6, and 8 chiplet versions of Rome. Milan has been only 4 or 8 chiplets so far; other configurations are asymmetric. This device appears to just have one quadrant of the IO die disabled, so 6 chiplets (192 MB L3) and 6 channel memory. The 6 active cores per chiplet is likely to fit in the power envelope.

Now that you mention it, one of the AMD execs mentioned ability to have 6 channels of memory turned on - sometimes during Milan launch - that some customers were asking for it.

I was thinking it was very odd back then, who would be asking for that. So it appears that this Facebook deal may have been brewing for some time and it was Facebook who asked for this functionality.

 

[moinmoin]

3D V-Cache in any case is an unexpected upgrade for AM4. Remember AMD originally said the AM4 platform will be supported through 2020. A chip with 3D V-Cache will need to be competitive to still launch this late, and it coming to AM4 in 2022 is nice for the platform's longevity.

 

[Mopetar]

Saying a CPU is 15% in games does NOT equal "this thread is about gaming cpus". Its about a new bunch of AMD CPUs, get it ? And what does 15% faster have to do with price premium ? Again, you are twisting words.

Damn. Here I was going to use that logic to talk about the performance of some old PC100 DDR DIMMS in this thread since they were 64 MB.

Anyhow, back on topic.

We know that Zen3D will V-cache, but will we get v-cache standard with Zen 4, at least on top-end models? From the testing on AL, we know that DDR5 can have significant performance uplifts in situations where bandwidth is important.

To what extent should we expect V-cache to compliment the inclusion of DDR5 or to what extent does moving to DDR5 reduce the impact of having V-cache? We know that AMD has the option of including it, or not, and I'm wondering what the product mix will look like.

Even if it's a smaller impact (at least for gaming) with DDR5 you'd have to imagine AMD would have a least a few top-end CPUs that utilize it just to run up the numbers a bit without turning the power up to Intel levels.

 

[Joe NYC]

Damn. Here I was going to use that logic to talk about the performance of some old PC100 DDR DIMMS in this thread since they were 64 MB.

Anyhow, back on topic.

We know that Zen3D will V-cache, but will we get v-cache standard with Zen 4, at least on top-end models? From the testing on AL, we know that DDR5 can have significant performance uplifts in situations where bandwidth is important.

To what extent should we expect V-cache to compliment the inclusion of DDR5 or to what extent does moving to DDR5 reduce the impact of having V-cache? We know that AMD has the option of including it, or not, and I'm wondering what the product mix will look like.

Even if it's a smaller impact (at least for gaming) with DDR5 you'd have to imagine AMD would have a least a few top-end CPUs that utilize it just to run up the numbers a bit without turning the power up to Intel levels.

Mike Clark of AMD said in the Anandtech interview that upcoming CPU designs will be flexible in having or not having V-Cache, so it will not be standard, it will be optional.

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Also, the V-Cache Zen 4 may follow some months after standard Zen 4, based on TSMC roadmap for N5 bottom die (H2 2022, IIRC).

BTW, there were some rumors of potential 170W TDP for select AM5 CPUs (unconfirmed).

It would be interesting if AMD released a separate Gaming oriented set of SKUs, with higher TDP and with V-Cache.

 

[Ajay]

Also, the V-Cache Zen 4 may follow some months after standard Zen 4, based on TSMC roadmap for N5 bottom die (H2 2022, IIRC).

BTW, there were some rumors of potential 170W TDP for select AM5 CPUs (unconfirmed).

It would be interesting if AMD released a separate Gaming oriented set of SKUs, with higher TDP and with V-Cache.

I'd rather hope Zen4 is sufficiently fast enough in games that no V-Cache is necessary. While V-Cache sounds exciting, I don't think it's going to be worth it, pricewise, as it will be a Halo product.

 

[LightningZ71]

V-cache, more than anything, is a hedge against DDR5 ram on socket AM4 AT THIS TIME and in the DESKTOP market. In the future, and in servers, it makes general sense.

 

[nicalandia]

I'd rather hope Zen4 is sufficiently fast enough in games that no V-Cache is necessary. While V-Cache sounds exciting, I don't think it's going to be worth it, pricewise, as it will be a Halo product.

Milan-X and many HPC workloads benefits from extra $ not just games

 

[Joe NYC]

I'd rather hope Zen4 is sufficiently fast enough in games that no V-Cache is necessary. While V-Cache sounds exciting, I don't think it's going to be worth it, pricewise, as it will be a Halo product.

Depends on the premium AMD charges for the V-Cache. I suggested (above) that it may very well turn out that the price premium will b 15% (approximately equal to performance increase in gaming).

Which I think would be a decent deal. Typically, with CPUs, the price scaling curve is steeper than corresponding performance scaling. Although, in the era of multi-core processors, it is not as bad as in the past with single core processors.

 

[Ajay]

Milan-X and many HPC workloads benefits from extra $ not just games

Yeah, should have specified that I meant client, not server.

 

[jamescox]

3D V-Cache in any case is an unexpected upgrade for AM4. Remember AMD originally said the AM4 platform will be supported through 2020. A chip with 3D V-Cache will need to be competitive to still launch this late, and it coming to AM4 in 2022 is nice for the platform's longevity.

It would be interesting to know the history there; roadmaps change though. I would expect that the v-cache was originally intended for Epyc only since it can make a massive difference in server applications. Perhaps this was like the original Threadripper that started out as a kind of a pet project. Maybe it turned out that the v-cache containing chips came out cheap enough that they make sense for desktop parts. Milan-x (Epyc 7003V?) will be really expensive, but that doesn’t really mean that the individual chips are that much more expensive. The current large cache per core parts (7xF3) variants come at a rather large price premium, but they are all 8 die variants with 1, 2, 3, or 4 cores active per CCD.

I might be out of the loop; haven’t had much time lately. Are the rumors saying that there will be an updated Zen 3+ type part in addition to the v-cache part? If so, is the v-cache part supposed to includ the updated cpu die or the current cpu die? For Milan, I would expect that they would go conservative and keep the same die as current Zen 3. If they are different base cpu die, then that might be interesting.

 

[maddie]

It would be interesting to know the history there; roadmaps change though. I would expect that the v-cache was originally intended for Epyc only since it can make a massive difference in server applications. Perhaps this was like the original Threadripper that started out as a kind of a pet project. Maybe it turned out that the v-cache containing chips came out cheap enough that they make sense for desktop parts. Milan-x (Epyc 7003V?) will be really expensive, but that doesn’t really mean that the individual chips are that much more expensive. The current large cache per core parts (7xF3) variants come at a rather large price premium, but they are all 8 die variants with 1, 2, 3, or 4 cores active per CCD.

I might be out of the loop; haven’t had much time lately. Are the rumors saying that there will be an updated Zen 3+ type part in addition to the v-cache part? If so, is the v-cache part supposed to includ the updated cpu die or the current cpu die? For Milan, I would expect that they would go conservative and keep the same die as current Zen 3. If they are different base cpu die, then that might be interesting.

With the discovery of TSVs being in Zen3 all along, it appears that it was always a possibility. I would imagine that the actual 7nm SoIC start-use-date was uncertain when Zen3 was finalized, so no mention until now.

 

[Joe NYC]

It would be interesting to know the history there; roadmaps change though. I would expect that the v-cache was originally intended for Epyc only since it can make a massive difference in server applications. Perhaps this was like the original Threadripper that started out as a kind of a pet project. Maybe it turned out that the v-cache containing chips came out cheap enough that they make sense for desktop parts. Milan-x (Epyc 7003V?) will be really expensive, but that doesn’t really mean that the individual chips are that much more expensive. The current large cache per core parts (7xF3) variants come at a rather large price premium, but they are all 8 die variants with 1, 2, 3, or 4 cores active per CCD.

I might be out of the loop; haven’t had much time lately. Are the rumors saying that there will be an updated Zen 3+ type part in addition to the v-cache part? If so, is the v-cache part supposed to includ the updated cpu die or the current cpu die? For Milan, I would expect that they would go conservative and keep the same die as current Zen 3. If they are different base cpu die, then that might be interesting.

I don't have an exact recollection (it may have come from one of the leakers) but apparently the B2 stepping will completely replace the B0 stepping. Which should cover everything from desktop to server, with V-Cache, and without V-Cache.

What I don't understand is why there is such a dearth news and curiosity about this B2 stepping...

B2 stepping should be functionally the same, but may have some optimization to allow slightly higher frequency, lower voltage / power consumption? Just a speculation.

It's probably staying on N7, not N6, because it would have leaked by now. (Although, IIRC, in the latest Datacenter presentation, AMD spelled out Mi200 is on N6, Genoa on N5, but said nothing about Milan X, so the door is not 100% shut).

 

[DrMrLordX]

BTW, there were some rumors of potential 170W TDP for select AM5 CPUs (unconfirmed).

There were some AM5 platform documents leaked from one of the mobo OEMs if I recall correctly. That's where people saw possible PPTs of up to 170W for AM5. Whether or not AMD actually launches a sku with that PPT is anyone's guess.

 

[LightningZ71]

Given that current speculation puts barcelo on N7 still, its a shame that it's not on N6. A shrink for yield on a process with better power characteristics with further power tweaks would have been ideal.

 

[jpiniero]

Given that current speculation puts barcelo on N7 still, its a shame that it's not on N6. A shrink for yield on a process with better power characteristics with further power tweaks would have been ideal.

Gives AMD additional supply.

 

[Kedas]

Gives AMD additional supply.

Going to N6 gives additional supply, I think if everyone moved from 7nm to 6nm TSMC could output about 20% more. (and maybe with better yield)
There isn't really something about improved silicon performance. (or at least not worth mentioning)

Being in short supply a move to 6nm could still be a good move, but that depends on their contracts. (and expected lifetime)

 

[eek2121]

Going to N6 gives additional supply, I think if everyone moved from 7nm to 6nm TSMC could output about 20% more. (and maybe with better yield)
There isn't really something about improved silicon performance. (or at least not worth mentioning)

Being in short supply a move to 6nm could still be a good move, but that depends on their contracts. (and expected lifetime)

TSMC only has so much capacity for a given process. Splitting up products between N5, N6, and N7 is actually the best play.

 

[Kedas]

TSMC only has so much capacity for a given process. Splitting up products between N5, N6, and N7 is actually the best play.

I could be wrong but it's my understanding that 6nm and 7nm use for a big part the same production line, steps of 7nm are replaced with 6nm steps. (resulting in total less steps)

 

[Doug S]

I could be wrong but it's my understanding that 6nm and 7nm use for a big part the same production line, steps of 7nm are replaced with 6nm steps. (resulting in total less steps)

Yes, that's my understanding as well. Their plan seems to be to upgrade lines from N7 to N6 and encourage as many customers as possible to port their designs, so that utilization of N7 drops since N6 is cheaper for customers and more efficient for TSMC everyone wins. Not sure how automated that "port" is, what it costs, and if the benefits are such that TSMC would be willing to fund those costs itself in some cases. Even if TSMC was willing to fund 100% of the cost for everyone they would always have to maintain some N7 capacity because it isn't worth it in certain markets with a lot of regulatory overhead where a product using the "same" chip built on N6 instead of N7 would have to be requalified.

N5 to N4 is the same thing, in that TSMC wants those using N5 longer term to move to N4.