Info 64MB V-Cache on 5XXX Zen3 Average +15% in Games

[Kedas]

Well we know now how they will bridge the long wait to Zen4 on AM5 Q4 2022.
Production start for V-cache is end this year so too early for Zen4 so this is certainly coming to AM4.
+15% Lisa said is "like an entire architectural generation"

 

[leoneazzurro]

Van Gogh development has quite probably been totally paid by Valve, so it does not matter how big the volume is. Barcelo is a OEM part going in cheap DDR4 laptops, so it will have some volume for sure.

 

[leoneazzurro]

In the meanwhile, the B2 stepping appears on MSI's motherboard support:

MAG X570S TORPEDO MAX

Powered by AMD Ryzen 5000 series processors, the MSI MAG X570S TORPEDO MAX is hardened with performance essential specifications to outlast enemies. Tuned for better performance by Core boost, DDR4 Boost, Premium Thermal Solution, M.2 Shield Frozr

www.msi.com

 

[biostud]

Maybe the B2 stepping involves some minor changes/rearrangements of the layout that makes it possible to implement 3D cache?
(pure speculation)

 

[DrMrLordX]

Maybe the B2 stepping involves some minor changes/rearrangements of the layout that makes it possible to implement 3D cache?
(pure speculation)

TSVs for cache stacking have been in Vermeer since the beginning.

 

[HurleyBird]

TSVs for cache stacking have been in Vermeer since the beginning.

Also Matisse.

 

[Joe NYC]

TSVs for cache stacking have been in Vermeer since the beginning.

But it is quite likely that it was not put through full set of real tests with V-Cache some 2+ years ago, when that design taped out, and new issues were found when real V-Cache was attached...

 

[DrMrLordX]

But it is quite likely that it was not put through full set of real tests with V-Cache some 2+ years ago, when that design taped out, and new issues were found when real V-Cache was attached...

There is no evidence to support that.

 

[maddie]

But it is quite likely that it was not put through full set of real tests with V-Cache some 2+ years ago, when that design taped out, and new issues were found when real V-Cache was attached...

You do know that there are experimental chips produced long in advance of official node & packaging startup?

 

[Joe NYC]

There is no evidence to support that.

Just speculation... If we see any V-Cache models without B2 stepping we can rule it out.

 

[maddie]

Just speculation... If we see any V-Cache models without B2 stepping we can rule it out.

Nope.

 

[Joe NYC]

Nope.

Nope to what?

 

[maddie]

Nope to what?

Actually, on re-reading, I misinterpreted your post. You are correct.

 

[biostud]

There is no evidence to support that.

AMD said that the B2 stepping was a minor revision.

AMD's Robert Hallock confirmed that the B2 stepping does not bring any architectural change but a new stepping generally results in better overall stability & clock output versus what we currently have in the market. Users who get the B2 stepping might or might not see any significant changes but we haven't seen a large sample size of these chips in the market yet and once they become more common, we will start seeing if the new revision has some advantages over the B1 stepping.

Weiterleitungshinweis

www.google.com

 

[jpiniero]

I think it's the idea that B2 is mainly bug fixes or other improvements related to the vcache and is no real improvement to non-vcache models.

 

[Ajay]

AMD clearly downplayed B2 on purpose. Maybe we should just believe them. It's just a minor stepping change. That's it.

 

[DrMrLordX]

I think it's the idea that B2 is mainly bug fixes or other improvements related to the vcache and is no real improvement to non-vcache models.

We have no idea if cache stacking would have worked with older steppings. We never will know. TSMC wasn't ready to produce stacked N7 regardless. All future Vermeer will be B2 stepping whether or not they are Zen3D.

 

[Mopetar]

It's quite likely it would have given AMD would have needed to do extensive testing to be able to bring an actual product to market. They've had actual performance figures so either this new stepping has existed for quite a long time or the stacked cache has worked to some degree since the hardware has supported it. I wouldn't doubt that the design has been iterated on and improved, but it doesn't make a lot of sense for it to not have worked at all prior to this new stepping.

 

[uzzi38]

Also Matisse.

No evidence of it in the Matisse die shots.

 

[AtenRa]

Since AMD said that Zen 3D will have the same high as with the plain Zen 3 die, then it is logical to believe that the old die cannot be the same that it is used in the 3D chip.
Unless im missing something else here.

 

[Joe NYC]

Since AMD said that Zen 3D will have the same high as with the plain Zen 3 die, then it is logical to believe that the old die cannot be the same that it is used in the 3D chip.
Unless im missing something else here.

AMD is planning reducing the height of the silicon, mechanically shaving off a layer of silicon equal in height to the chip being stacked. This stacked chip, being put on the top, will be extremely thin.

 

[AtenRa]

AMD is planning reducing the height of the silicon, mechanically shaving off a layer of silicon equal in height to the chip being stacked. This stacked chip, being put on the top, will be extremely thin.

I dont believe they have any clearance to machine anything on top of the current die in order to put the stacked L3 chip for then the final product to be at the same height as before.

 

[Joe NYC]

I dont believe they have any clearance to machine anything on top of the current die in order to put the stacked L3 chip for then the final product to be at the same height as before.

The height of a single layer is ~50 microns.

 

[Hitman928]

I dont believe they have any clearance to machine anything on top of the current die in order to put the stacked L3 chip for then the final product to be at the same height as before.

They reduce height on the silicon substrate at the bottom of the die but since these are flip chips, it is the "top" of the die. For a CMOS process, a typical substrate thickness is around 700 um (give or take a couple hundred micron), so for a single stack you need to cut that in approximately half to get the same height as without the stack.

 

[Hitman928]

The height of a single layer is ~50 microns.

That's the minimum height TSMC said they can do but AMD won't be going that thin with Zen3d since they are just doing a single stack.

 

[IEC]

I'm prepared for Zen3D. Bought a B550 Unify board with seriously overkill VRMs (14+2, 90A each) and more than enough m.2 NVMe slots (4) for me to finally upgrade to some Gen4 goodness. B550 flagship at midrange pricing ($219) was just too good to pass up.