http://www.chip-architect.com/news/ontario_vs_atom.jpg
No reason to believe the setup won't be similar on Kabini (everything doubled).
No reason to believe the setup won't be similar on Kabini (everything doubled).
Nemesis 1
Lifer
- Dec 30, 2006
- 11,366
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YEP and I get that NOW . LOL I retract everthing I said about intel core sizes . I can't believe I struggled with that . without catching on to those small measurements . oops!
The pics were pretty tho I am looking into the core and seeing everthing there . and missing the fact that haswell is 185mm2. lol
The pics were pretty tho I am looking into the core and seeing everthing there . and missing the fact that haswell is 185mm2. lol
Thank you Hans for posting, I appreciate your current and past analysis on cpu die sizes.
If you haven't checked out hans website you might want to go view it quickly he has other cpu die size analysis for over a decade.
If you haven't checked out hans website you might want to go view it quickly he has other cpu die size analysis for over a decade.
You are completely incorrect -- that is not the attitude that is generally held on these forums. Stop with the straw man pity party.
Anyways, here's a die shot of Ontario/Zacate
www.ixbt.com/cpu/images/amd-bobcat/bobcat-die-hq.jpg
Great post Hans. Too bad you didn't compare PD.
What's interesting to me is AMD's situation.
Kabini is 21% of Haswell. Haswell is not 5x faster, is it?
PD is 30.9mm^2 (on 32nm mind you) for a module or slightly larger than Haswell per core except 2 cores share the front end and FP. Oranges to oranges, PD is what, 7x Kabini?
In such case, how does it make any sense to have BD/PD/SR based APUs? On the same die size budget, Kabini can fit the same iGPU PLUS an entire 8790M assuming the uncore is the same size (which we know it isn't). Esp. by 2014 everything is on 28nm.
Moreover, if an engineering team work on improving 3.1mm^2 of silicon, shouldn't they be able to extract a higher % improvement than if they have to cover off 7x the silicon? Well we already know the answer re Kabini vs Brazos.
Last but not least, under what possible scenario is silicon 7x larger going to be more efficient power wise?
Which begs the question: why is AMD pouring any resources into BD when they are so far behind in every imaginable metric, when they could allocate those resources to Kabini where they are ahead and where their schwerpunkt lies? At the very very least, these guys should not be running 2 BD programs (Trinity and Vishera).
AMD is crazy.
What's interesting to me is AMD's situation.
Kabini is 21% of Haswell. Haswell is not 5x faster, is it?
PD is 30.9mm^2 (on 32nm mind you) for a module or slightly larger than Haswell per core except 2 cores share the front end and FP. Oranges to oranges, PD is what, 7x Kabini?
In such case, how does it make any sense to have BD/PD/SR based APUs? On the same die size budget, Kabini can fit the same iGPU PLUS an entire 8790M assuming the uncore is the same size (which we know it isn't). Esp. by 2014 everything is on 28nm.
Moreover, if an engineering team work on improving 3.1mm^2 of silicon, shouldn't they be able to extract a higher % improvement than if they have to cover off 7x the silicon? Well we already know the answer re Kabini vs Brazos.
Last but not least, under what possible scenario is silicon 7x larger going to be more efficient power wise?
Which begs the question: why is AMD pouring any resources into BD when they are so far behind in every imaginable metric, when they could allocate those resources to Kabini where they are ahead and where their schwerpunkt lies? At the very very least, these guys should not be running 2 BD programs (Trinity and Vishera).
AMD is crazy.
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few things,
1. BD/PD is broken in several important locations (instruction fetch, decode, L1D write, L1I) , you can't uses its current performance as a base for what a Core taking that amount of silicon performs like. Judge that off SR.
2. IPC gets harder and harder to extract the more you have
3. Transistors are basically "free" these days, performance per mm unless massively different isn't really a worth while metric to count.
4. you don't stop because of one failure otherwise no one would do anything.
5. moving data costs lots of power, that's why performance CPU's are getting bigger and bigger because its all about minimizing data movement, predicting where data needs to be etc. Thats why CPU's with more transistors can still be way more power efficient the ones with fewer transistors.
1. BD/PD is broken in several important locations (instruction fetch, decode, L1D write, L1I) , you can't uses its current performance as a base for what a Core taking that amount of silicon performs like. Judge that off SR.
2. IPC gets harder and harder to extract the more you have
3. Transistors are basically "free" these days, performance per mm unless massively different isn't really a worth while metric to count.
4. you don't stop because of one failure otherwise no one would do anything.
5. moving data costs lots of power, that's why performance CPU's are getting bigger and bigger because its all about minimizing data movement, predicting where data needs to be etc. Thats why CPU's with more transistors can still be way more power efficient the ones with fewer transistors.
There was nothing about Vishera announced.
In all honesty, I personally think that the next FX chip should be an "excavator" based one.
Unless they decide to kill off non-APU's tho. Which, I wouldn't mind either.
Without being able to normalize for the associated development costs, we can't really make any justified analysis of what either team should have been able to accomplish.
In the industry we speak to this as "entitlement", project managers and their funding managers know they can't expect blood from a stone. You are only entitled to expect a given return on your R&D investment if you actually made that R&D investment in the first place.
Give the Kabini team 1/10 the resources as you did the Brazos team and you are not entitled as a business to expect the Kabini team to out-deliver what the Brazos team delivered.
Conversly, give the Kabini team 10x the resources you did the Brazos team and you are entitled as a business to expect the Kabini team to out-deliver what the Brazos team delivered.
We can make all the comparisons we like between the two products, but in the absence of knowing their associated development costs we cannot reliably make a reasonable analyses of what should have happened, could have happened, ought to have happened, etc.
We don't know what level of entitlement the Kabini team was resourced to deliver to the managing directors. They may have over-delivered despite being under-resources, or they may have under-delivered despite being over-resourced...we will never know unless someone very high up in AMD who would be privy to the big picture numbers decided to make them public and tell us about it.
(Like IBM did with the 45nm CELL shrink)
Nehalem core 24.4mm2 -> SB core 18.4mm2 -> Haswell core 14.5mm2.
Smaller each gen... despite increased IPC, clock and power efficiency. I'd love to see that kind of x86 performance inside an iPad-like tablet real soon.
Surface Pro is a nice step in that direction.
Smaller each gen... despite increased IPC, clock and power efficiency. I'd love to see that kind of x86 performance inside an iPad-like tablet real soon.
Surface Pro is a nice step in that direction.
ShintaiDK
Lifer
- Apr 22, 2012
- 20,378
- 145
- 106
Nehalem core 24.4mm2 -> SB core 18.4mm2 -> Haswell core 14.5mm2.
Smaller each gen... despite increased IPC, clock and power efficiency. I'd love to see that kind of x86 performance inside an iPad-like tablet real soon.
Surface Pro is a nice step in that direction.
Smaller and smaller. It might be more correctly to count transistors as well. Since some cores are designed larger both from performance and heat reasons. A Kabini core would most likely vaporize if it got the same wattage as a FX module.
Nemesis 1
Lifer
- Dec 30, 2006
- 11,366
- 2
- 0
Depends AVX2 it could be more than 5x faster, An example of what Intel bought with purchase of elbrus, Of course intel had to refine but this is what they bought.Its also an example of doing more with fewer transitors . Its a shame intel is the only company that has access to this tech . Sure AMD can use the instruction set. But with AVXII its all most useless as the vec prefix only works with intel software and hardware . AMD does not nor will not every have access to this hardware software as its patiented.
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IDC, I assumed from discussions on another site that Brazos and thus Kabini had a smaller team. I could be wrong. I'm not saying one team is better than the other either.
What I am saying kabini is already ahead of Trinity on TDP, on size (half), and probably on performance up to 20W. Some of that advantage relates to "better" integration (uncore, GPU, FCH) which of course can be duplicated (though not without some time and $$$).
The core is the fundamental difference and just like with ARM, small is beautiful seems to apply here: its cheaper, faster to improve, more room to improve, consumes less power, and has a much bigger TAM.
From an opportunity cost of engineering resources pov, its a complete waste for AMD to assign any resources to Big Core APUs like Kaveri and Richland (and to treat SR like anything but the small TAM that it is).
From a competitive standpoint, its utter craziness. Kabini leads Intel in size, TDP, integration and GPU (which they've always had) whereas they are losing badly in those other segments.
But we need not worry, AMD Mgmt always makes the wrong decisions, even when the gold mine is at their feet.
if AMD had balls instead of going 2x256 with EX they should go 4X128, take the scheduling/power/256bit op hit and dominate SSE. its not like there going to have a problem with Decode.
inf64
Diamond Member
- Mar 11, 2011
- 3,702
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The problem is their design TDP budget. Even with shared unit like that which can do 2x128bit FMA they are hitting the power wall at around ~4Ghz on 32nm SOI node.Maybe with a bit of tweaking they could manage to get another 100-200Mhz out of PD, but that's it(counting only full core clock speed during FMA/AVX workload,not Turbo/power management tricks).
After they remove some of the power limitations (hopefully with 28nm) we may see some improved FP performance. SR core is supposedly having slimmed down FP unit in which 1 "MMX" pipe got axed . But now ,again supposedly, FMACs can execute integer SSE (a reshuffle of pipeline if you will)so they can help speed up the common integer SSE workloads. Still, the total FP throughput of the core will probably be similar to what PD can do, per clock. Only with EX core we may see 2x256bit FMAC configuration per module and this core will be on 20nm and hopefully arriving 1 year after SR(so 2015).
Vesku
Diamond Member
- Aug 25, 2005
- 3,743
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Except when you need that extra performance small can't get you. Which is why companies pushing pure mobile, small, low power devices are also pimping embracing client-server for the consumer in the form of "cloud" utilities. They'll be running that bigger and more power hungry equipment for you and piping it via the internet. It's been a bumpy ride since even internal company implementations of client-server have all sorts of issues to this day even after creeping past the half century mark. In fact the security, stability and such issues have mainly grown in complexity.
I think that's why we get an extra helping of "space food pill"-esque marketing when it comes to these kinds of consumer areas, same as how some people over compensate when trying to get away with something.
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