Sounds interesting, so what does this mean in practice. All Zen7 CPUs will have some V-Cache (or other type of similar cache?), but smaller in size than on X3D SKUs?
Not all Zen 7 SKUs. The only one shown with this design would be the dense server CCD.
It means no L3 in the main compute die, and L3 access always going across to the other die.
Going from current Zen6 Dense die (which does not have a V-Cache option), comparable Zen7 Dense SKU would have 2x L3 (~8MB), less of the very expensive die (A14) wasted on SRAM.
So a win-win for that SKU, but this is not transferable to other Zen 7 SKUs.
Also, is it not using traditional X3D tech, but instead something more similar to NVL-S bLLC?
It is using same hybrid bond. The similarity with NVL bLLC is that the extra cache is always part of the unit, unlike V-Cache being optional.
But a 2 die solution, where 1 die is expensive and 2nd die is cheaper may offer some additional rebalancing.
There may be opportunities for this type of division of labor in client, but nothing so far has been leaked as far a stacking.

