Discussion Zen 7 speculation thread

[igor_kavinski]

mythical "rentable units".

 

[Joe NYC]

Yeah there's MI450X with nerfed Vector FP64 and no Matrix FP64 and MI430X with double rate Vector FP64, Matrix FP64 and no Matrix FP4/6.

It seems like AMD may have some prospective supercomputer bids in progress.

AMD may be the only game in town when it comes to scientifically oriented supercomputers, after Intel withdrew itself following the Aurora disaster, and NVidia is too busy counting the money from AI. (And its cards have nerved FP64 even more than before)

 

[adroc_thurston]

CDNA1/2/3/4 have many architecture advancements that are not in RDNA2/3/4 because they are in a completely different architecture branch.

Works the opposite way too, RDNA SIMD and cachemem models are far, far superior.

 

[OneEng2]

While Lisa Su said (at recent AI summit) that some new AI tools will allow AMD faster release schedule, you expect a slow down, Zen 7 taking 50% longer than any other Zen releases.

What are your reasons for this? Why do you think you have a better idea about AMD release schedule than Lisa?

Hmm. Let's see here. Who is currently ahead in performance? Yea, AMD .... and from a node behind no less.

Who just wet the bed with PTL yields? Yep.

Lets look at WHY companies design new processors. It isn't because they screwed up the engineering on the current generation. It's because new process technology has come along that enables higher transistor density and thus larger transistor budget in the same die area. This transistor budget is used to improve the performance.

Since process technology is slowing down rapidly, so will performance increases. It's just math.

I will say that AMD has been working very smart with TSMC. Chiplets, 3D stacked cache, etc. These are all great ways to do more with less.

To directly answer your question though, I don't think AMD is going to feel any pressure to release Zen 6 ..... rather on Zen 7.

The way things are going over at Intel, I wouldn't be surprised if AMD sold most of its desktop and laptop models on N3P and didn't even bother with N2 except for DC. With no threat of 18A and 14A (high NA) to push them, I think AMD will resort to profit taking .... like any company would.

 

[Joe NYC]

Hmm. Let's see here. Who is currently ahead in performance? Yea, AMD .... and from a node behind no less.

Who just wet the bed with PTL yields? Yep.

Lets look at WHY companies design new processors. It isn't because they screwed up the engineering on the current generation. It's because new process technology has come along that enables higher transistor density and thus larger transistor budget in the same die area. This transistor budget is used to improve the performance.

Speaking of Transistor Densities, AMD has been delivering CPU / GPU chip dies with insane transistor densities, higher than its peers.

IMO, this could be a data point that AMD is employing (well) some AI tools.

Since process technology is slowing down rapidly, so will performance increases. It's just math.

I will say that AMD has been working very smart with TSMC. Chiplets, 3D stacked cache, etc. These are all great ways to do more with less.

To directly answer your question though, I don't think AMD is going to feel any pressure to release Zen 6 ..... rather on Zen 7.

The way things are going over at Intel, I wouldn't be surprised if AMD sold most of its desktop and laptop models on N3P and didn't even bother with N2 except for DC. With no threat of 18A and 14A (high NA) to push them, I think AMD will resort to profit taking .... like any company would.

I don't think AMD is going to take the foot off the gas pedal. There are the Arm hordes, Arm itself, hyperscalers using Arm, NVidia using Arm.

Volume is what accelerates the profits. Being a small minor player in number of markets - most importantly client laptop, and then, of course datacenter GPU, the easiest way to greater profit is to gain market share, to move up from being a bit player.

In fact, AMD is doing the opposite of what you suggest - to reach the state where I think more profits are:

In datacenter GPU, AMD has moved to N3P with Mi355 ahead of NVidia which is using N4P, in order to gain more share in the market. And later, in 2026, NVidia moves only to N3P and AMD moves to N2P on Mi400.

 

[MadRat]

NVidia has always been several steps behind leading edge, because it didn't pay to lead.

 

[OneEng2]

Speaking of Transistor Densities, AMD has been delivering CPU / GPU chip dies with insane transistor densities, higher than its peers.

IMO, this could be a data point that AMD is employing (well) some AI tools.




I don't think AMD is going to take the foot off the gas pedal. There are the Arm hordes, Arm itself, hyperscalers using Arm, NVidia using Arm.

Volume is what accelerates the profits. Being a small minor player in number of markets - most importantly client laptop, and then, of course datacenter GPU, the easiest way to greater profit is to gain market share, to move up from being a bit player.

In fact, AMD is doing the opposite of what you suggest - to reach the state where I think more profits are:

In datacenter GPU, AMD has moved to N3P with Mi355 ahead of NVidia which is using N4P, in order to gain more share in the market. And later, in 2026, NVidia moves only to N3P and AMD moves to N2P on Mi400.

I think that any company with a comfortable lead will take the foot off the gas. It's called profit taking.

If AMD can maintain a lead without releasing a new processor on a new node, they will do it.

In the case of nVidia, AMD is NOT in the lead. Still your point is valid. in DC where AMD is in the lead, they are paying out the nose for the leading edge process .... but then again, in DC it is worth every penny!

 

[Cheesecake16]

Yeah there's MI450X with nerfed Vector FP64 and no Matrix FP64 and MI430X with double rate Vector FP64, Matrix FP64 and no Matrix FP4/6.

So are they going to be diverging the ALU design between MI450X and MI430X?
Because as of CDNA2 the ALUs are 64b native ALUs not 32b native ALUs... so they would need a different ALU design in order to do what you are suggesting without it still physically being there...

 

[Kepler_L2]

So are they going to be diverging the ALU design between MI450X and MI430X?
Because as of CDNA2 the ALUs are 64b native ALUs not 32b native ALUs... so they would need a different ALU design in order to do what you are suggesting without it still physically being there...

Yeah these are the FMA rates AFAIK:

 

[Cheesecake16]

Yeah these are the FMA rates AFAIK:
View attachment 128428

So... if it's the 1/32 like you said then it should be 8 FMA per cycle per CU for GFX1250...

I am also going to question that they are getting rid of the extra ALU lanes that GFX1200 has along with cutting the matrix performance significantly... By the math you have there, assuming it's FMA ops per cycle per CU and not FLOPS per cycle per CU, then they are cutting the FP16/BF16 Matrix performance in half compared to CDNA4... If you are talking about the FMAs per clock then it's a halving of the FP8, FP6, and FP4 Matrix FLOPs per cycle and a quartering of the FP16/BF16 Matrix performance compared to CDNA4...

And I am doubtful that they are going to spend the RnD time for the different GFX125X ALUs... That isn't AMD's style...

I personally think you are extrapolating far too much from Github repos...

 

[511]

Speaking of Transistor Densities, AMD has been delivering CPU / GPU chip dies with insane transistor densities, higher than its peers.

IMO, this could be a data point that AMD is employing (well) some AI tools.

yeah they are using densest libraries available with more metal layers to get a denser but performant as well

 

[soresu]

It seems like AMD may have some prospective supercomputer bids in progress.

Given they have managed to get in at least 2 of the last faster supercomputers that isn't a stretch.