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Discussion Zen 7 speculation thread

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adroc_thurston said:
They literally killed Turin AI.
It's not happening.
Click to expand...

Turin AI was supposed to be AI chiplet to substitute for CPU chiplet.

What @LightningZ71 is talking about is probably one of those NPU blocks on the IOD, similar to what Strix and Kraken have.

Adding such an NPU would open the door for AMD to get these into corporate desktops, rather than using repurposed APUs in desktop.
 
Joe NYC said:
Turin AI was supposed to be AI chiplet to substitute for CPU chiplet.
Click to expand...
Yeah.
Joe NYC said:
What @LightningZ71 is talking about is probably one of those NPU blocks on the IOD, similar to what Strix and Kraken have.
Click to expand...
That's never happening.
It's dead Si in a place where it matters most.
Joe NYC said:
Adding such an NPU would open the door for AMD to get these into corporate desktops, rather than using repurposed APUs in desktop.
Click to expand...
what.
EPYCs are not going into desktops.
 
adroc_thurston said:
Yeah.

That's never happening.
It's dead Si in a place where it matters most.

what.
EPYCs are not going into desktops.
Click to expand...

We have NPUs on monolithic chips, AMD has talked about a possibility of selling a discrete NPU.

I wonder why not a NPU chiplet? If AMD is already doing InFO packaging, additional expense would not be high, and AMD would have an option of including it (with some CPUs) and not including it (saving die area and money).

Or updating the SKUs when MSFT thinks of the new requirements, by just replacing the NPU chiplet...
 
Joe NYC said:
We have NPUs on monolithic chips
Click to expand...
It's a useless slab of dark Si.
Joe NYC said:
AMD has talked about a possibility of selling a discrete NPU
Click to expand...
Worthless. They sell Versal AI already anyway.
Joe NYC said:
I wonder why not a NPU chiplet?
Click to expand...
Worthless.
Joe NYC said:
Or updating the SKUs when MSFT thinks of the new requirements, by just replacing the NPU chiplet...
Click to expand...
Honestly I have some harrowing news for you for the Zen7 era.
 
adroc_thurston said:
It was an off-the-record remark.
Click to expand...
Remark is a funny way of classifying what sounded very overtly like a long term product development strategy.

If this wasn't real then I'd imagine he got a pretty nasty reprimand if not a pay cut - and if it is real and the information release wasn't approved I'd imagine the same.
 
soresu said:
Remark is a funny way of classifying what sounded very overtly like a long term product development strategy.

If this wasn't real then I'd imagine he got a pretty nasty reprimand if not a pay cut - and if it is real and the information release wasn't approved I'd imagine the same.
Click to expand...
People misunderstood what "UDNA" meant. It's not a single architecture across gaming and datacenter, but a unification of the development pipeline.

CDNA1/2/3/4 have many architecture advancements that are not in RDNA2/3/4 because they are in a completely different architecture branch.

With "UDNA" strategy, development follows a gaming->datacenter->gaming pattern, where advancements from one type of architecture can be re-integrated into the next if they make sense, but the architectures are still different as they don't need to have the same features (i.e gaming doesn't need strong FP64 or extremely large matrix cores, datacenter doesn't need RT/Texture/Geometry/Raster features).
 
I suppose if AI is designing it then you can throw in all sorts of design inputs to let it game outcomes until its as close to ideal as possible. Imagine taking the worst thermal components and being able to build in 3-dimensions so that they reside in top layers where they can be more easily cooled, while less thermally limited circuits get located at the bottom. Your circuits that emit EMF could conveniently be placed where their emissions cancel out magnetically, but in other places get woven chirally to concentrate in places where they can recycle the energy. Maybe it locks down excess voltage by treating the heatsink as its wireless charger to an integrated recycler circuit.
 
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