Discussion Zen 7 speculation thread

[Gideon]

This is a fair point:

https://twitter.com/x/status/1952690059087343987

I'd also rather have a "breaking change" at some point, forcing a new bracket to coolers, if the IHS will be thinner/better.

 

[Joe NYC]

They literally killed Turin AI.
It's not happening.

Turin AI was supposed to be AI chiplet to substitute for CPU chiplet.

What @LightningZ71 is talking about is probably one of those NPU blocks on the IOD, similar to what Strix and Kraken have.

Adding such an NPU would open the door for AMD to get these into corporate desktops, rather than using repurposed APUs in desktop.

 

[adroc_thurston]

Turin AI was supposed to be AI chiplet to substitute for CPU chiplet.

Yeah.

What @LightningZ71 is talking about is probably one of those NPU blocks on the IOD, similar to what Strix and Kraken have.

That's never happening.
It's dead Si in a place where it matters most.

Adding such an NPU would open the door for AMD to get these into corporate desktops, rather than using repurposed APUs in desktop.

what.
EPYCs are not going into desktops.

 

[Joe NYC]

Yeah.

That's never happening.
It's dead Si in a place where it matters most.

what.
EPYCs are not going into desktops.

We have NPUs on monolithic chips, AMD has talked about a possibility of selling a discrete NPU.

I wonder why not a NPU chiplet? If AMD is already doing InFO packaging, additional expense would not be high, and AMD would have an option of including it (with some CPUs) and not including it (saving die area and money).

Or updating the SKUs when MSFT thinks of the new requirements, by just replacing the NPU chiplet...

 

[adroc_thurston]

We have NPUs on monolithic chips

It's a useless slab of dark Si.

AMD has talked about a possibility of selling a discrete NPU

Worthless. They sell Versal AI already anyway.

I wonder why not a NPU chiplet?

Worthless.

Or updating the SKUs when MSFT thinks of the new requirements, by just replacing the NPU chiplet...

Honestly I have some harrowing news for you for the Zen7 era.

 

[Joe NYC]

Honestly I have some harrowing news for you for the Zen7 era.

What, AMD doing matrix math inside the CPU chiplet?

 

[adroc_thurston]

What, AMD doing matrix math inside the CPU chiplet?

No.

 

[igor_kavinski]

No.

The NPU becomes bigger than the compute chiplet?

 

[Joe NYC]

No.

Merging GPU and NPU would be the most logical thing to do.

Which means we can't have that. This is Microsoft, we are talking about...

 

[adroc_thurston]

The NPU becomes bigger than the compute chiplet?

No.

Merging GPU and NPU would be the most logical thing to do.

That's called having MFMA in shader cores and guess what has it.

 

[Joe NYC]

No.

That's called having MFMA in shader cores and guess what has it.

MFMA making its way from CDNA to RDNA? Or merging into the UDNA?

That would be which generation? Presumably past RDNA5

 

[adroc_thurston]

MFMA making its way from CDNA to RDNA

Yeah.

Or merging into the UDNA?

What's that

 

[Joe NYC]

Yeah.

What's that

UDNA is AMD's "rentable unit"

 

[soresu]

What's that

A better question is what was an AMD official doing talking about something which apparently doesn't exist as if it was a near term product?

 

[adroc_thurston]

UDNA is AMD's "rentable unit"

What

A better question is what was an AMD official doing talking about something which apparently doesn't exist as if it was a near term product?

It was an off-the-record remark.

 

[soresu]

It was an off-the-record remark.

Remark is a funny way of classifying what sounded very overtly like a long term product development strategy.

If this wasn't real then I'd imagine he got a pretty nasty reprimand if not a pay cut - and if it is real and the information release wasn't approved I'd imagine the same.

 

[Win2012R2]

UDNA is AMD's "rentable unit"

MLID is that you...

 

[Joe NYC]

MLID is that you...

No, but I was referring to MLID, who spend inordinate amount of time talking the mythical "rentable units".

I came across a great meme on it but I can't find it anymore.

 

[Kepler_L2]

Remark is a funny way of classifying what sounded very overtly like a long term product development strategy.

If this wasn't real then I'd imagine he got a pretty nasty reprimand if not a pay cut - and if it is real and the information release wasn't approved I'd imagine the same.

People misunderstood what "UDNA" meant. It's not a single architecture across gaming and datacenter, but a unification of the development pipeline.

CDNA1/2/3/4 have many architecture advancements that are not in RDNA2/3/4 because they are in a completely different architecture branch.

With "UDNA" strategy, development follows a gaming->datacenter->gaming pattern, where advancements from one type of architecture can be re-integrated into the next if they make sense, but the architectures are still different as they don't need to have the same features (i.e gaming doesn't need strong FP64 or extremely large matrix cores, datacenter doesn't need RT/Texture/Geometry/Raster features).

 

[Win2012R2]

i.e gaming doesn't need strong FP64

Looks like FP64 is up for the chop overall

 

[Kepler_L2]

Looks like FP64 is up for the chop overall

MI450X has same 1:32 ratio for FP64 as gaming GPUs, MI430X on the other hand actually has double rate FP64.

 

[Win2012R2]

MI430X on the other hand actually has double rate FP64.

I see, so AMD does not want to give up HPC then, nice!

 

[Joe NYC]

Looks like FP64 is up for the chop overall

Dylan Patel "leaked" one of the configurations of Mi400 (I think Mi430) datacenter GPU that will be HPC oriented, without nerfing of FP64.

 

[Kepler_L2]

Dylan Patel "leaked" one of the configurations of Mi400 (I think Mi430) datacenter GPU that will be HPC oriented, without nerfing of FP64.

Yeah there's MI450X with nerfed Vector FP64 and no Matrix FP64 and MI430X with double rate Vector FP64, Matrix FP64 and no Matrix FP4/6.

 

[MadRat]

I suppose if AI is designing it then you can throw in all sorts of design inputs to let it game outcomes until its as close to ideal as possible. Imagine taking the worst thermal components and being able to build in 3-dimensions so that they reside in top layers where they can be more easily cooled, while less thermally limited circuits get located at the bottom. Your circuits that emit EMF could conveniently be placed where their emissions cancel out magnetically, but in other places get woven chirally to concentrate in places where they can recycle the energy. Maybe it locks down excess voltage by treating the heatsink as its wireless charger to an integrated recycler circuit.