Verano is a village with barely 1000 inhabitants, i doubt that it was ever mentioned elsewhere than in this thread, they just made a typo out of Verona since that s a big city that is close to Venice.Well, why wouldn't AMD use the Verano name for new EPYC series or why would that be a mistake?If that city didn't exist, it would be quite logical to assess it as a mistake in marketing presentation. So you have two cities Verona and Verano, so now we can have a beer in Verano.
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Discussion Zen 7 speculation thread
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Yes, that 40% IPC bubble is Zen 5's trademark.
Yes, but... reading the Chips'n'Cheese profiled data, majority of stalls within the Zen 5 core are caused by the frontend latency.
This metric is hugely flawed. Capacitance/frequency optimization, weird IO stuff, niche features, etc. Specifically, Zen 5 invested a notable amount of transistors to support the AVX-512 full-speed data flow.
Even that 13% is not so impressive for such ambitious design, right? I know the relative base value of Zen 4 was higher than Zen 1's but still - there are Apple and Qualcomm.
Those sizes are cool, but how about the int RF or ROB size?
At 448 slots Zen 5's ROB is still smaller than Golden Cove's 512, let alone Lion Cove's 576.
The same applies to 240 int RF vs 280-300 of Intel's.
Both limits manifest themselves in the profiled data.
fastandfurious6
Banned
the results:
this stuff sells..... decision makers see big number and make decision.....
zen6 gonna fix all quirks and latency..... zen5 got rushed
Well, it surely sells to AVX-512 shops. Like AMX sells to whatever AI shops.
fastandfurious6
Banned
cloud providers........ gazillions of orders
It's not something AMD exclusive unlike Client CPUs
There's very rarely any official data for anything like this.
Using area is a much better metric IMO.
marees
Platinum Member
It is zen6+ (despite the misleading site name, Charlie is usually accurate)
Update June 16, 2025 @ 945am: Well we screwed this up, and we blame chronic lack of sleep last week coupled to ultra-short time lines to write up the info. Verano is _NOT_ the successor to Venice, it is a Venice variant. Florence is Venice+1, something we knew and should have remembered before writing the above paragraph.
AMD Lays Out their MI350, MI400, and MI500 Roadmap
At AMD’s Advancing AI event, they laid out the roadmap for future AI GPUs and racks.
www.semiaccurate.com
Asterox
Golden Member
If you look at the classic Geekbench test, you get a much broader picture. Roughly speaking, Zen 5 brings an average of 100% better singlecore and multithread CPU score.
If you take average numbers, that would roughly be the comparison.
If all the L3 is placed outside the die using vCache, I would definitely expect AMD to raise core counts for Zen 7. In fact, I would think double.... or as many as they could feed with bandwidth and the power of their socket limitation at the time.
I wouldn't be surprised if both AMD and Intel start producing new designs ONLY ever 2 nodes. They might just do a "refresh" every half node (or quarter node 😉). It doesn't make sense to redesign without an increase in transistor budget IMO.
If that is the case, then Zen 6 could show some interesting IPC improvements by freeing this up and having a lower latency IOD as well.
... and lots of applications today in DC can take advantage of AVX512... so it isn't just marketing, it really makes a difference.
Well then .... that makes a great deal of sense. I definitely can't see Zen 7 before 2028 .... maybe 2029 unfortunately.
While Lisa Su said (at recent AI summit) that some new AI tools will allow AMD faster release schedule, you expect a slow down, Zen 7 taking 50% longer than any other Zen releases.
What are your reasons for this? Why do you think you have a better idea about AMD release schedule than Lisa?
fastandfurious6
Banned
exactly!!!! said that few weeks ago and everyone here was like "but we don't know, AMD doesn't confirm anything" lol
everyone uses AI for both r&d and development lmao, it's a pure accelerator no frills just works. only needs pair of senior eyes and strong QA/testing (also enhanced by AI) to detect the unavoidable hallucinations
The second decode cluster is only when SMT is active it doesn't work in ST. C&C even postulates it is essentially a return of clustered multi-threading in Bulldozer.
Most of the gains are due to the new ISA, not the 512-bit path.
Without the 512-bit but keeping the 256-bit path you get +29%.
For power/area efficiency it makes sense to have AVX512-256.
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Exactly. When I posted this in another thread (with link to the video where Lisa said it) someone replied that AMD will only do it for datacenter GPUs.
Which makes zero sense. If you develop tools to accelerate your work, you will deploy the same tools across all the divisions, across the product stack.
And for AMD, which has such a wide portfolio of products, AMD can get the best return on the investment into these tools.
And you don't need "heavy branching" to make clustered decode work. Branching happens quite often enough that Tremont reaches 6-wide quite often even without the load balancer.
gdansk
Diamond Member
Not what I said at all. If you'd like to be charitable go read it again. But to reiterate:
1. ML has been used in hardware design for sometime. Cadences didn't improve instead have become worse. Why?
2. Design complexity grows. Often beyond any increase in productivity.
3. MI is getting more resources. It should have more overlapping work and could have a shorter cadence.
And obviously the Zen teams are doing far more work on producing variants and proliferation of SKUs into more niches than they were before. I don't expect the cadence to improve.
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I always felt like AMD saw potential vulnerabilities in Zen5's design in the later engineering stages causing them to preemptively disable parts of the silicon to prevent exploitation.
gdansk
Diamond Member
No, it's pretty good. People are just expecting too much exploitable ILP. Despite all the changes Zen is still limited by the frontend and it is (allegedly) the most difficult part of an x86 chip.
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I just don't think that AMD hit their goals they were expecting too tbh.
TBF, Zen 5's tock just does not seem great. Esp in comparison to Zen 3.
gdansk
Diamond Member
That's how fruit are picked.
LNC wasn't a bad tock either. That's just how fruit are picked.
itsmydamnation
Diamond Member
Zen5 is very different/odd compared to everyone else.
They went and built way bigger bones but then kept the muscle at zen4+ size.
if i remember it was supposed to be on 3N , so it ended up being a bigger sized core on 4N.
it seems the balance mantra is still king and they aren't in a rush to take all the sugar many other cores have ( ROB/reg file size ).
im guessing they would have targeted higher clocks on 4N and some larger internal structures and then Zen5 would have been more inline with typical.
here is hoping for Zen6 to spend 2 gens of sugar at once + good clock boost to boot.
if i was a betting man Zen 7's probably gonna but Zen5 plus a bit style up lift.
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