Question Zen 6 Speculation Thread

[adroc_thurston]

Subtweet: A comment on competitiveness of Arm vs. x86, especially in orchestrating GPU tasks to improve GPU utilization

Well that's mostly down to server Tegra being crap.

Substack article about hyperscalers vertical integration ability to compete with Merchant silicon in both CPU and GPU

Tougher than it looks yes.

 

[Tachyonism]

Potential config for the Medusa Point line up.

Doesnt seems like what we know/heard so far?

 

[Joe NYC]

Potential config for the Medusa Point line up.

Doesnt seems like what we know/heard so far?
View attachment 138314

That's what MLID leaked some time ago. Like a year ago.

 

[MerryCherry]

Potential config for the Medusa Point line up.

Doesnt seems like what we know/heard so far?
View attachment 138314

Windows scheduler is going to have a stroke.

 

[gdansk]

It'll probably have the highest Linux vs NT performance delta of any part AMD has ever designed.
Can't wait to see it.

 

[Markfw]

Potential config for the Medusa Point line up.

Doesnt seems like what we know/heard so far?
View attachment 138314

That not big.little the way Intel does it. Zen6c is just s little less cache, the core otherwise is the same.

 

[adroc_thurston]

That not big.little the way Intel does it. Zen6c is just s little less cache, the core otherwise is the same.

True ISA-wise, but from the sched POV freq delta puts them into way different perf tiers.

 

[Markfw]

True ISA-wise, but from the sched POV freq delta puts them into way different perf tiers.

But capability is the same. for example when Intel started this avx-512 was in big, but not little. The current titles are the same in general, the capability is not there is the little for some features.

edit: so the same code can run on any core, just runs slower on c core threads.

 

[Covfefe]

But capability is the same. for example when Intel started this avx-512 was in big, but not little. The current titles are the same in general, the capability is not there is the little for some features.

edit: so the same code can run on any core, just runs slower on c core threads.

All of the cores in a big.LITTLE CPU have to support the same ISA. There's never a case where some code can run on one core but not another.

 

[Doug S]

All of the cores in a big.LITTLE CPU have to support the same ISA. There's never a case where some code can run on one core but not another.

They don't HAVE to. For example if you wanted to make a core without AVX512 or heck if you really want to get crazy without any SIMD/FP at all you could do it. Just have it trap when an instruction it doesn't support is encountered and reschedule it on a core that do support it (plus set a flag in the scheduler to insure it that process doesn't ever get scheduled on the cut down core ever again)

Not saying it really makes sense to do this today (because the "gain" from a stripped down core in terms of area/power/performance isn't worth providing enough SIMD/FP free work for it) but the one constant in the computing world is that things change so never say never. Maybe someday we can make photonic processors that run an order of magnitude faster than current technology but our "transistor equivalent" budget is multiple orders of magnitude less so we have to pick and choose what it supports.

 

[Covfefe]

They don't HAVE to. For example if you wanted to make a core without AVX512 or heck if you really want to get crazy without any SIMD/FP at all you could do it. Just have it trap when an instruction it doesn't support is encountered and reschedule it on a core that do support it (plus set a flag in the scheduler to insure it that process doesn't ever get scheduled on the cut down core ever again)

Not saying it really makes sense to do this today (because the "gain" from a stripped down core in terms of area/power/performance isn't worth providing enough SIMD/FP free work for it) but the one constant in the computing world is that things change so never say never. Maybe someday we can make photonic processors that run an order of magnitude faster than current technology but our "transistor equivalent" budget is multiple orders of magnitude less so we have to pick and choose what it supports.

Interesting, do you have any examples of CPUs that work this way?

 

[itsmydamnation]

Interesting, do you have any examples of CPUs that work this way?

None I Know of, amd have multiple patients for it.

 

[Doug S]

Interesting, do you have any examples of CPUs that work this way?

Didn't Intel had a CPU generation where they had big cores that were designed to support AVX512 and little cores that weren't, and they ended up shipping it with AVX512 disabled in the big cores? So they might have experimented with it and decided it wasn't worth the trouble, or maybe Microsoft told them to pound sand when they said they wanted this kind of thing in the Windows Scheduler so they had no choice.

 

[biostud]

Didn't Intel had a CPU generation where they had big cores that were designed to support AVX512 and little cores that weren't, and they ended up shipping it with AVX512 disabled in the big cores? So they might have experimented with it and decided it wasn't worth the trouble, or maybe Microsoft told them to pound sand when they said they wanted this kind of thing in the Windows Scheduler so they had no choice.

Yeah, and if you disabled the little cores you could activate AVX512 on the big cores IIRC.

 

[Thunder 57]

Didn't Intel had a CPU generation where they had big cores that were designed to support AVX512 and little cores that weren't, and they ended up shipping it with AVX512 disabled in the big cores? So they might have experimented with it and decided it wasn't worth the trouble, or maybe Microsoft told them to pound sand when they said they wanted this kind of thing in the Windows Scheduler so they had no choice.

Yeah, and if you disabled the little cores you could activate AVX512 on the big cores IIRC.

The original Alder Lake worked this way.

 

[Markfw]

The original Alder Lake worked this way.

Yes, and I had one. I think it was a 12700k, but correct me if I am wrong on the model number. and I did disable the little cores and ran a avx-512 app and it started taking 300 watts ! (per my kill-a-watt)

 

[LightningZ71]

Relaxing the PT a bit for stacked parts is pretty easy.
Also they did build PVC and are doing CWF et al so they're familiar with thermals in 3D at least.

Familiar, yes. The difference being that server applications run at significantly lower frequencies with far more manageable hot spots as a result. The thermal load from, for example, Nova lake's P core running at 6+Ghz is going to be savagely harder to deal with than a 64 core title running at sub 5Ghz. I'm sure that there is a solution, but is it an ECONOMICAL one?

 

[LightningZ71]

Yes, and I had one. I think it was a 12700k, but correct me if I am wrong on the model number. and I did disable the little cores and ran a avx-512 app and it started taking 300 watts ! (per my kill-a-watt)

It was potentially the best consumer AVX 512 offering up to that point and until Zen4 was about the best you'd get. Tiger Lake H was decent per clock, but didn't get up there very well. I always wondered what they could have squeezed out of an honest attempt at making 12 P Bartlett Lake a high performance part.

 

[Markfw]

It was potentially the best consumer AVX 512 offering up to that point and until Zen4 was about the best you'd get. Tiger Lake H was decent per clock, but didn't get up there very well. I always wondered what they could have squeezed out of an honest attempt at making 12 P Bartlett Lake a high performance part.

well, I think that power usage is out of the park. I sold it right after that. I got a Zen 3, and then when Zen 4 came out, it could do avx-512 using WAY less power. My 53 core Zen 4 just hits that on 64 cores, not 8.

 

[LightningZ71]

Our amplifiers go up to 11, see? We were the loudest because of that!

 

[adroc_thurston]

The difference being that server applications run at significantly lower frequencies with far more manageable hot spots as a result.

Oh no my friend, GPUs have nightmarish hotspots too.
See AMD heatmap for MI300 (it's from HC'23 or '24 I forgot which one).

 

[LightningZ71]

I thought CWF is a server CPU package? I didn't think PVC ever really went anywhere but a handful of HPC projects outside of the very late Aurora.

 

[adroc_thurston]

I thought CWF is a server CPU package? I didn't think PVC ever really went anywhere but a handful of HPC projects outside of the very late Aurora.

Me point is they have more than enough experience modeling nightmarish hotspots too.

 

[Makaveli]

If they don't have X3D "available" at launch it'll be disappointing

It's never been available at launch why would that change now?

 

[gdansk]

It's never been available at launch why would that change now?

Necessity