Question Zen 6 Speculation Thread

[LightningZ71]

Keep in mind, vanilla Zen 6 CCDs are an aggregate L3 cache upgrade over vanilla Zen5. That 50% L3 boost WILL show up in a few games that get benchmarked. Existing games won't suddenly need more cores, but they will appreciate having more local L3 to work out of. It won't make up the difference to the 3d cache parts, but it will help.

 

[Hulk]

From Zen 5 to Zen 6 the front and back ends were opened up significantly. I would be surprised if Zen 6 became any wider. But I do think there will be substantial changes to the structures the keep the decode units and exe ports occupied. Namely cache improvements, the ubiquitious branch prediction improvements, OoO scheduling, more registers and buffers,improved logic to better keep those decoders and ports filled...etc.

This architectural advancement schedule from AMD would make sense. If Zen 4 was a balanced design then improving on those internal structures without making the part wider wouldn't do much if the front and back end were already nearing capacity. But making Zen 5 getting wider would show benefit even without substantially upgrading the parts mentioned above. Zen 6 will "rebalance" Zen 5 and put all of that width to use I'm thinking.

 

[Fjodor2001]

That's not the point.
And >95% of desktop users will use the new CPUs only for gaming (and lesser tasks that benefit even less from more than 12C/24T).

No, it's exactly the point. It's 48T and you can use it for whatever you want. And both AMD and Intel think there'll be sufficient market for such SKUs to be released, otherwise it would not be in their lineup.

As for Intel, ALL their SKUs will be 16C or above except the bottom one in the NVL-S lineup. Clearly shows that more cores is the path forward from their point of view.

ntel is doing it because brute-force MT is their only chance to win any benchmarks.
AMD is doing it in part to counter Intel for marketing reasons, in part to make some extra pocket money from that small niche of people who do other stuff than gaming.

That doesn't change the fact that these will make up maybe 1% of volume and 2-3% of desktop revenue, if not less, and are irrelevant for gaming, which is THE main purpose of buying a faster CPU for every normal desktop PC buyer/upgrader.

In fact, I fully expect in this cycle more people will go for mono-CCD models, and less sales for dual-CCD models compared to previous gens, because mono-12C is a decent MT upgrade vs. 8C without the caveats of dual-CCDs.
I can absolutely see 7900X and 9900X owners, possibly even 7950X owners "downgrading" to the Ryzen 7 580X or whatever AMD will call the 12C mono-CCD vanilla model.

Both AMD and Intel will be going for 48T CPUs. They would not be doing so unless they think there will be sufficient market for it. As for your percentage numbers, it's absolutely ridiculous you have nothing to back it up, otherwise provide links.

 

[adroc_thurston]

And both AMD and Intel think there'll be sufficient market for such SKUs to be released, otherwise it would not be in their lineup.

AMD doesn't. but they gotta throw leaky 12c bins somewhere.

They would not be doing so unless they think there will be sufficient market for it.

It's salvage.

 

[Fjodor2001]

AMD doesn't. but they gotta throw leaky 12c bins somewhere.

So AMD thinks there is a market for 48T after all. Again, otherwise it would not be in their DT lineup.

It's salvage.

It's reality.

 

[adroc_thurston]

So AMD thinks there is a market for 48T after all.

They would toss it out anyway, market or not. You gotta do something with leaky bins.

Again, otherwise it would not be in their DT lineup.

where else would I stash leaky 12c 5%er bins?

 

[Fjodor2001]

They would toss it out anyway, market or not. You gotta do something with leaky bins.

Waddaya mean leaky bins?

And regardless, they expect there to be sufficient number of people that want and buys the 48T SKUs, otherwise they would not release it. So there's a market for it.

where else would I stash leaky 12c 5%er bins?

You can call them whaddever you want. They think there's a market for 48T on DT.

 

[adroc_thurston]

Waddaya mean leaky bins?

what it says on the box.

they expect there to be sufficient number of people that want and buys the 48T SKUs, otherwise they would not release it

no. They just gotta stash leaky bins somewhere.

They think there's a market for 48T on DT.

They don't have to think.
DT is like a garbage dump for AMD.

 

[mmaenpaa]

Waddaya mean leaky bins?

And regardless, they expect there to be sufficient number of people that want and buys the 48T SKUs, otherwise they would not release it. So there's a market for it.

You can call them whaddever you want. They think there's a market for 48T on DT.

Higher quality chips that are binned generally have less leakage. Less leakage = less voltage. less voltage = lower heat = in Epyc it goes

 

[Hulk]

But the leaky ones are the ones that clock higher.

 

[Fjodor2001]

what it says on the box.

Says nothing about that on the box, otherwise clarify.

no. They just gotta stash leaky bins somewhere.

They are expecting there to be demand for 48T on DT and that they will be sold, otherwise they would not have them in the lineup.

They don't have to think.
DT is like a garbage dump for AMD.

Yeah for the CCDs with not all cores working. But those are not used on 48T SKUs.

 

[adroc_thurston]

Says nothing about that on the box

Sure does.

They are expecting there to be demand for 48T on DT

nope lmao. they gotta dump leaky bins somewhere.

Yeah for the CCDs with not all cores working. But those are not used on 48T SKUs.

you're 3 inches away from discovering parametric yield.
so close, yet so far.

 

[Timorous]

Says nothing about that on the box, otherwise clarify.

They are expecting there to be demand for 48T on DT and that they will be sold, otherwise they would not have them in the lineup.

Yeah for the CCDs with not all cores working. But those are not used on 48T SKUs.

Just because all the cores work does not mean they work at the voltages required to hit the TDP limits in server chips.

Those that do not hit the requirements go in desktop and the really bad ones can be the poor CCD in the dual CCD configs.

 

[LightningZ71]

Barnacles!

Dies that go into EPYC processors must meet certain requirements for power consumption at certain target clocks. If they have otherwise functional CCDs that can't hit that spec, they are used for desktop products that have MUCH more relaxed requirements for power consumption at certain clocks instead focusing on peak achievable clocks at reasonable voltage levels.

As time goes on and overall yield metrics improve and as that generation's demands for EPYC CCDs are more readily met, better bins make it to the desktop. Sometimes, they make it into higher spec parts like the 5959XT, or the 9850X3D.

AMD can either throw CCDs away that don't meet EPYC requirements, or they can use an already developed platform to sell them under to recover cost of production. Current 12 and 16 core Ryzen parts make up a very small percentage of overall sales of each generation, and certainly not enough of a market to justify product development for fully bespoke parts, but is enough marginal sales to cover dev costs to sell below spec CCDs.

 

[adroc_thurston]

or the 9850X3D

Well you see, no.
WoW bonding means they can't pre-sort KGDs, meaning 9850X3D is the top 20% (probably) of 9800X3D bins. A separate binning pool basically.

 

[DrMrLordX]

Anyone remember the FX9590? That was a leaky chip!

 

[basix]

12C will be a nice upgrade. Also for gamers, when looking and shader compilation times when you install new drivers

But sure, higher IPC and clock-rates together with a bigger L3$ are very nice upgrades for gaming. I am also very curious how the improvements regarding memory subsystem will show up in gaming performance. Zen 5 is pretty much latency bound (frontend, DRAM). Bigger INT reg-files, wider OoO window, improved frontend and DRAM latency. Everything of that is very nice for latency hiding / reduction and therefore also gaming workloads.

 

[Geddagod]

From Zen 5 to Zen 6 the front and back ends were opened up significantly. I would be surprised if Zen 6 became any wider. But I do think there will be substantial changes to the structures the keep the decode units and exe ports occupied. Namely cache improvements, the ubiquitious branch prediction improvements, OoO scheduling, more registers and buffers,improved logic to better keep those decoders and ports filled...etc.

This architectural advancement schedule from AMD would make sense. If Zen 4 was a balanced design then improving on those internal structures without making the part wider wouldn't do much if the front and back end were already nearing capacity. But making Zen 5 getting wider would show benefit even without substantially upgrading the parts mentioned above. Zen 6 will "rebalance" Zen 5 and put all of that width to use I'm thinking.

L1i + BPU improvements look sorely needed from perf monitoring events.
Wonder how PPC is going to scale with Zen 6's alleged nice frequency bump. It's not as if Zen 6 has particularly large caches or anything...
Will the mesh still run at core clocks since core clocks are apparently getting a large bump?

 

[MS_AT]

BPU

What kind of improvements do you have in mind?

 

[adroc_thurston]

L1i + BPU improvements look sorely needed from perf monitoring events.

BPU no (already class-leading by a country mile), L1i maybe.

It's not as if Zen 6 has particularly large caches or anything...

Doesn't need 'em.

Will the mesh still run at core clocks since core clocks are apparently getting a large bump?

yeah sure.

 

[Hulk]

L1i + BPU improvements look sorely needed from perf monitoring events.
Wonder how PPC is going to scale with Zen 6's alleged nice frequency bump. It's not as if Zen 6 has particularly large caches or anything...
Will the mesh still run at core clocks since core clocks are apparently getting a large bump?

Based on the article below Zen 6 is going to be more revolutionary than evolutionary. I have a feeling they are starting with dispatch and execution of Zen 5 and reworking everything around that . L3 will of course be larger with more cores/CCD. I think they will keep 1:1 for mesh and core clocks but will decouple when it's advantageous from a power point-of-view. It seems like Zen from the beginning hasn't look super incredible on paper in many ways, but it works with real code. Intel has often looked amazing on paper, but not lived up to the paper's hype. It's almost like Intel theorizes about what "should" work and builds it while AMD just does a lot of testing and builds what actually works, regardless what the theory says in some cases. I think at the end of the day Intel designs will often have higher maximum performance on very niche workloads and sacrifice big time in other areas, like gaming. AMD on the otherhand performs well across the board.

AMD publishes first Zen 6 document detailing ground-up redesign on 2nm process node — brand-new 8-wide CPU core with strong vector capabilities

But there are a few catches.

www.tomshardware.com

 

[adroc_thurston]

Based on the article below Zen 6 is going to be more revolutionary than evolutionary. I have a feeling they are starting with dispatch and execution of Zen 5 and reworking everything around that . L3 will of course be larger with more cores/CCD. I think they will keep 1:1 for mesh and core clocks but will decouple when it's advantageous from a power point-of-view. It seems like Zen from the beginning hasn't look super incredible on paper in many ways, but it works with real code. Intel has often looked amazing on paper, but not lived up to the paper's hype. It's almost like Intel theorizes about what "should" work and builds it while AMD just does a lot of testing and builds what actually works, regardless what the theory says in some cases. I think at the end of the day Intel designs will often have higher maximum performance on very niche workloads and sacrifice big time in other areas, like gaming. AMD on the otherhand performs well across the board.

AMD publishes first Zen 6 document detailing ground-up redesign on 2nm process node — brand-new 8-wide CPU core with strong vector capabilities

But there are a few catches.

www.tomshardware.com

No it's a normal derived core.

 

[reaperrr3]

As for Intel, ALL their SKUs will be 16C or above except the bottom one in the NVL-S lineup. Clearly shows that more cores is the path forward from their point of view.

No. It means that
- Intel P cores got too fat and power-hungry to use more than 8 of them and still remain competitive in clocks and MT perf/W
- removing SMT was dumb, especially from a marketing perspective

 

[StefanR5R]

I can use 48t for whatever I want? Nice! Is Microsoft rewriting the W11 Explorer context menu to be 48-threaded, such that it will pop up as quick again as it did in W10?

On another matter,

Based on the article below Zen 6 is going to be more revolutionary than evolutionary.

Anton Shilov wrote on December 20: "AMD this week released a document titled "Performance Monitor Counters for AMD Family 1Ah Model 50h-57h Processors" (discovered by InstLatX64) that reveals numerous architectural details of AMD's Zen 6-based CPUs, including the EPYC 'Venice' processor for data centers, through performance monitoring interfaces. As it turns out, Zen 6 is not exactly an evolution of Zen 5, but rather an all-new design with a different ideology." — Correction: As it turns out, A. Shilov hasn't read the document, or at least not understood any of it. Which is OK if one isn't a low-level systems programmer, but it's not OK to then go on and make up bogus commentary.

 

[LightningZ71]

Well you see, no.
WoW bonding means they can't pre-sort KGDs, meaning 9850X3D is the top 20% (probably) of 9800X3D bins. A separate binning pool basically.

Then that leads to this question: how does AMD/TSMC determine which CCDs are "Leaky" and unsuitable for EPYC usage if they have no way of testing them before they get bonded to a package? Do they batch all the CCDs from each wafer, drop one into a test substrate, test that single CCD, then bin the rest of the batch based on that single result?