Question Zen 6 Speculation Thread

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Fjodor2001

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Just. Stop.
He's big headed sure. But it's obvious that AMD weren't considering offering 3DX2. Adroc doesn't, and doesn't claim to, have knowledge of AMDs internal margins and defect rates. Sure, he speaks in absolutes, but anyone smart can see that AMD must be feeling this is just a way to wring some more money out of enthusiasts, while their process is mature and there's zero competition from Intel. A business decision has changed, and recently. You need to get over it. You're as bad as he is with your definites, and you add even less to the conversation than he does.
Stop.
Stop with the damage control already. He made a claim that 9950X3D2 would never happen (based on speculation or whatever). It turned out to be incorrect. Simple as that.
 
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Fjodor2001

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the PS6 is still 8c/16t + 2 lp cores.

That’s a major indicator
That's just speculation / rumors. But if we are to speculate, there's also X-Box next gen "Magnus" with 3xZen6 + 8xZen6c = 11C/22T rumored:

 

marees

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soresu

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That's just speculation / rumors. But if we are to speculate, there's also X-Box next gen "Magnus" with 3xZen6 + 8xZen6c = 11C/22T rumored:

For sure 48 GB of RAM is just wanton hopium even without the AI mess.
 

Fjodor2001

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For sure 48 GB of RAM is just wanton hopium even without the AI mess.
Yeah, sounds high unless RAM prices will come down. But based on past track record they often release the consoles with very high tech specs for the time when they are released, since they are supposed to have a life time of ~7 years on the market. So they must have sufficiently high specs to survive and be meaningful for that long.

They've even sold at a loss initially at launch, since they count on making a profit later years when the price of the HW comes down.

By the way, the PS6 is also rumored to have similar RAM spec at (up to) 40 GB (which is close to the 48 GB speculated for the next X-box):

 

Win2012R2

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He simply said it would not happen.
Someone was WRONG on the Internet!!!
Zen6 12 core with V-Cache will thoroughly outclass 9950x3d2 with 16 cores - in gaming and many other tasks.
Yeah, but in 2027 - in the meantime they'll have something better than current stuff to sell in 2026.
But it's obvious that AMD weren't considering offering 3DX2
AMD actually said that they CONSIDERED it but decided not to offer it due to low benefit, it should have been a server chip though, higher margins, no mismatched chiplets.

They should have done it from start and they'd better do it for Zen6.
Adroc doesn't, and doesn't claim to, have knowledge of AMDs internal margins and defect rates
That's pretty easy to know (for 3D models) without having any inside info from AMD:

1) Margins: PHAT!
2) Defect rates: low
 
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Fjodor2001

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What is the cpu breakup for medusa premium? Any idea ??
By Medusa Premium, do you perhaps mean Medusa Halo? In that case we have this:


1766853786881.png

So for the CPU breakup:

2x Zen6 12C/24T = 24C/48T in total. Plus 2 Zen 6 LP cores.
 

marees

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By Medusa Premium, do you perhaps mean Medusa Halo? In that case we have this:


View attachment 135708

So for the CPU breakup:

2x Zen6 12C/24T = 24C/48T in total. Plus 2 Zen 6 LP cores.

No. Guys. By MDSP I mean MDSP only

Not interested in any of the other zen 6 skus
 

carrotmania

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Stop with the damage control already. He made a claim that 9950X3D2 would never happen (based on speculation or whatever). It turned out to be incorrect. Simple as that.
I was being polite before, but dang dude, you are an absolute bore. Stop derailing the thread cos some random dude said something about a product that is an obvious cash grab. It doesn't matter. No one else in this SPECULATION thread cares one bit. Put him on ignore and STFU.
 

LightningZ71

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Are people just being deliberately obtuse?

The 9950x3d2 is a marketing exercise. It's a specific SKU to compete against the NVL big L3 products. It exists specifically to defend the corner cases where you have high thread count programs where working sets spill out of the existing CCD L3, but will fit the 3d cache L3, to handle the cases where a process gets scheduled on the wrong CCD, to handle those few synthetic benchmarks that can benefit from having 3d cache on both CCDs.

NVL is bringing the kitchen sink, and AMD needs to defend their market with their own until they can ship Zen6. They have the capacity, might as well use it.

I still think that it would be better as an AM5 EPYC product though.
 
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adroc_thurston

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Are people just being deliberately obtuse?

The 9950x3d2 is a marketing exercise. It's a specific SKU to compete against the NVL big L3 products. It exists specifically to defend the corner cases where you have high thread count programs where working sets spill out of the existing CCD L3, but will fit the 3d cache L3, to handle the cases where a process gets scheduled on the wrong CCD, to handle those few synthetic benchmarks that can benefit from having 3d cache on both CCDs.

NVL is bringing the kitchen sink, and AMD needs to defend their market with their own until they can ship Zen6. They have the capacity, might as well use it.

I still think that it would be better as an AM5 EPYC product though.
uhhh brother, NVL ships *after* Olympic Ridge.
 

Fjodor2001

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I was being polite before, but dang dude, you are an absolute bore. Stop derailing the thread cos some random dude said something about a product that is an obvious cash grab. It doesn't matter. No one else in this SPECULATION thread cares one bit. Put him on ignore and STFU.
No you were being offensive from the start and you’re continuing down that path. We’re simply concluding that the claim that 9950X3D2 would never happen turned out to be incorrect. Just own it.
 

Joe NYC

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Are people just being deliberately obtuse?

The 9950x3d2 is a marketing exercise. It's a specific SKU to compete against the NVL big L3 products.

Probably not even that - related to NVL. It will be on the market for nearly a year prior to NVL shipments.

It's almost like AMD is printing cash with the V-Cache, and wants to print more.

What is still not known if this is just better binning or new stepping

I still think that it would be better as an AM5 EPYC product though.

Agreed, but:

1766864326261.png
 

marees

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Apr 28, 2024
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Is the Medusa Premium = Medusa Mini Halo?

I thought Medusa Premium was just Medusa 1 + 12 core CCD.
Yes — MDSP is the medusa mini halo

No — MDS-1 will have integrated rdna 3.5 as a monolithic die. MDS-P will have AT4 rdna 5 chiplet attached to it

But both MDS-1 & MDS-P will share the fp10 socket

MDS-1 is expected to have 4+4+2 as part of the monolithic die

MDS-P sure to have a cpu ccd. What will be the config of this ccd ?
 

Joe NYC

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Yes — MDSP is the medusa mini halo

No — MDS-1 will have integrated rdna 3.5 as a monolithic die. MDS-P will have AT4 rdna 5 chiplet attached to it

But both MDS-1 & MDS-P will share the fp10 socket

MDS-1 is expected to have 4+4+2 as part of the monolithic die

MDS-P sure to have a cpu ccd. What will be the config of this ccd ?

It seems to me that AMD will have only one standalone, 12 core Zen 6 CCD.

Then, the question is if some of these Halo SKUs will have 3 die implementations.

While it may make sense for the GPU chiplets to have the memory controller, it does not make sense for it to have things like Zen 6 LP cores, potentially other full Zen 6 cores and NPU. Considering these graphics chiplets may be offered as standalone, very low end GPUs.

So, it seems to me that there has to be a scaled down chiplet with LP cores, some other Zen 6 cores, IO, NPU but without GPU.
 
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marees

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It seems to me that AMD will have only one standalone, 12 core Zen 6 CCD.

Then, the question is if some of these Halo SKUs will have 3 die implementations.

While it may make sense for the GPU chiplets to have the memory controller, it does not make sense for it to have things like Zen 6 LP cores, potentially other full Zen 6 cores and NPU. Considering these graphics chiplets may be offered as standalone, very low end GPUs.

So, it seems to me that there has to be a scaled down chiplet with IO, NPU and without GPU.
Or tale magnus cpu & attach it to AT4 to get medusa premium that sits in the fp10 socket of medusa point-1 ??