Question Zen 6 Speculation Thread

[soresu]

But based on past track record they often release the consoles with very high tech specs for the time when they are released

How far back in the past are you thinking of?

From PS4/XB1 gen onward pretty much all console manufacturers low balled their specs to mid tier level in the first iteration of a generation.

Presumably due to troubles making back money on both R&D and BOM for state of the art tech

Nintendo in particular have been on the extreme end of that equation since Wii where they basically just started recycling old GameCube hardware with a shrink and more clock/cores for Wii and Wii U (+ old TeraScale GPU), and 2+ old gen hardware bought for cheap(er) with Switch 1 and 2.

 

[reaperrr3]

So, it seems to me that there has to be a scaled down chiplet with LP cores, some other Zen 6 cores, IO, NPU but without GPU.

Why?

8 RDNA3.5 CUs in N3P or N3C will be like 30% of the StrixPoint IGP in terms of area, something like 30-40mm².
Removing that physically doesn't save enough area to be worth an extra die, they'll just disable it for the MDS-Premium SKUs (not that I expect those to be particularly high-volume to begin with).

 

[Joe NYC]

Why?

8 RDNA3.5 CUs in N3P or N3C will be like 30% of the StrixPoint IGP in terms of area, something like 30-40mm².
Removing that physically doesn't save enough area to be worth an extra die, they'll just disable it for the MDS-Premium SKUs (not that I expect those to be particularly high-volume to begin with).

Then, do you also disable the memory controllers? Which die would then connect to the memory, the GPU die or MDS1 die?

Maybe one day I will have a Eureka, and I will understand all the reasons that went behind structuring of the Zen 6 / RDNA 5 client product line-up, but I still don't have that understanding. It seems like a hodge podge of differing ideas loosely related, barely overlapping with each other.

 

[Kepler_L2]

Then, do you also disable the memory controllers? Which die would then connect to the memory, the GPU die or MDS1 die?

Maybe one day I will have a Eureka, and I will understand all the reasons that went behind structuring of the Zen 6 / RDNA 5 client product line-up, but I still don't have that understanding. It seems like a hodge podge of differing ideas loosely related, barely overlapping with each other.

Olympic Ridge: IOD + CCD
Medusa Point: SoC + (optional) CCD
Medusa Premium: SoC + AT4 GMD
Medusa Halo: SoC + AT3 GMD

 

[Joe NYC]

Olympic Ridge: IOD + CCD
Medusa Point: SoC + (optional) CCD
Medusa Premium: SoC + AT4 GMD
Medusa Halo: SoC + AT3 GMD

Are these 3 different SoCs? 4, when counting Olympic Ridge IOD?

That's the part that's kind of bothers me. How many different dies does it take to have this complete line-up. It seems like 7.

It seems like the minimum, to cover this full line up, would be 5 different dies, so maybe I should just give up complaining...

Also, doesn't Medusa Halo have an optional CCD, as 3rd die?

Then, if AMD decides to launch AT3 and AT4 as standalone cards, does that die have everything it needs for full GPU, or would it also need some additional, limited IOD?

 

[Kepler_L2]

Are these 3 different SoCs? 4, when counting Olympic Ridge IOD?

Yes

That's the part that's kind of bothers me. How many different dies does it take to have this complete line-up. It seems like 7.

It seems like the minimum, to cover this full line up, would be 5 different dies, so maybe I should just give up complaining...

1 IOD, 1 CCD, 3 SoCs, 2 GMDs (which are also used for dGPUs)

Also, doesn't Medusa Halo have an optional CCD, as 3rd die?

Doubt that will become an actual product

Then, if AMD decides to launch AT3 and AT4 as standalone cards, does that die have everything it needs for full GPU, or would it also need some additional, limited IOD?

Just a MID for PCIe/Display

 

[Cheesecake16]

1 IOD, 1 CCD, 3 SoCs, 2 GMDs (which are also used for dGPUs)

So, just to be clear, Medusa Point, Medusa Premium, and Medusa Halo all have different SoC dies?

Doubt that will become an actual product

So then how many cores will Medusa Premium and Medusa Halo have then?

 

[Joe NYC]

Yes

1 IOD, 1 CCD, 3 SoCs, 2 GMDs (which are also used for dGPUs)

Doubt that will become an actual product

Just a MID for PCIe/Display

Thanks for clarifications / confirmations.

 

[adroc_thurston]

So, just to be clear, Medusa Point, Medusa Premium, and Medusa Halo all have different SoC dies?

MDS1/2/3 are like, the actual SoCs.
AT3/4 are dGPUs with CCDs taped to the side.

 

[marees]

MDS1/2/3 are like, the actual SoCs.
AT3/4 are dGPUs with CCDs taped to the side.

AT3 & AT4 taped to MDS1 SoC — plus optional 12p core ccd?

 

[adroc_thurston]

AT3 & AT4 taped to MDS1 SoC

oh ffs no.

plus optional 12p core ccd

god no nothing is optional.

 

[Claudiovict]

Medusa Halo is set to launch in 2027 or 2028? MLID says 2027, but Kepler said RDNA5 is going to be Mid 2027 and usually APUs take some time to launch after the GPUs

 

[marees]

oh ffs no.

god no nothing is optional.

Then you would need something between the ccd & gcd for MDS-P & MDS-H right ? What do you call that ?

 

[adroc_thurston]

Then you would need something between the ccd & gcd for MDS-P & MDS-H right ?

No.
Why would you?

 

[marees]

No.
Why would you?

Maybe lp cores ?

 

[marees]

No.
Why would you?

It would help if someone can draw the layout of MDSP & MDSH

 

[adroc_thurston]

Maybe lp cores ?

You can stash them in the GMD or MID just fine.

 

[adroc_thurston]

It would help if someone can draw the layout of MDSP & MDSH

 

[Fjodor2001]

Nintendo in particular have been on the extreme end of that equation since Wii where they basically just started recycling old GameCube hardware with a shrink and more clock/cores for Wii and Wii U (+ old TeraScale GPU), and 2+ old gen hardware bought for cheap(er) with Switch 1 and 2.

Yeah, I was talking about PS and X-Box. Nintendo has never (at least in the last few generations) gone for very high specs or tried compete with those two w.r.t. pure performance.

 

[Fjodor2001]

Article about the configs based on info from MLID (from August 2025):

AMD's next-gen 'Alpha Trion' (AT4/AT3) RDNA 5 GPU leaks: laptop LPDDR6 memory could be used

AMD's next-generation RDNA 5-based 'Alpha Trion 4' and 'Alpha Trion 3' aka AT4/AT3 specs leaked: desktop RDNA 5 cards rumored with laptop memory.

www.tweaktown.com

Also contains some info about CPU configs for those who wondered about that.

 

[marees]

Article about the configs based on info from MLID (from August 2025):

AMD's next-gen 'Alpha Trion' (AT4/AT3) RDNA 5 GPU leaks: laptop LPDDR6 memory could be used

AMD's next-generation RDNA 5-based 'Alpha Trion 4' and 'Alpha Trion 3' aka AT4/AT3 specs leaked: desktop RDNA 5 cards rumored with laptop memory.

www.tweaktown.com

View attachment 135728

Also contains some info about CPU configs for those who wondered about that.

As per MLID, MDSP & MDSH have different 12 core ccds

• Magnus — 3p + 8c
• Medusa premium — 4p + 8c
• Medusa halo — 12p

So its not going to be a purely 12p core ccd
There seems to be one more 4p + 8c ccd

@Tigerick what do you think ?

 

[Fjodor2001]

Medusa Point: SoC + (optional) CCD

MDS1 SoC — plus optional 12p core ccd?

god no nothing is optional.

So is there an optional 12C Zen6 CCD for Medusa Point or not? The MLID slide says there is.

 

[marees]

So is there an optional 12C Zen6 CCD for Medusa Point or not? The MLID slide says there is.

Medusa point 1 alone has an optional 12p ccd. This is known as medusa point-1 hi

Medusa point 3 is bumblebee. It doesn't have optional ccd

Medusa point 2 sits between 1 & 3 but no optional config. This is not on AMD's leaked roadmaps (unlike bumblebee) hence speculation is that it is 2028 or later depending TSMC nodes availability

So on FP10 socket we have

1. Medusa premium — 4p+8c ccd + mid with 2lp + AT4 GCD with 12wgp/24cu
2. Medusa point 1 high — 12p ccd + soc with 4p + 4c + 2lp + unknown rdna 3.5 CU
3. Medusa point 1 — soc with 4p + 4c + 2lp + unknown rdna 3.5 CU
4. Medusa point 2 — soc with less than 4/4/2 cpu & rdna 3.5 cu
5. Medusa point 3 (bumblebee) — soc with 2/2/2 & rdna 3.5 cu

 

[ETI4711]

1 IOD, 1 CCD, 3 SoCs, 2 GMDs (which are also used for dGPUs)

So on FP10 socket we have

1. Medusa premium — 4p+8c ccd + mid with 2lp + AT4 GCD with 12wgp/24cu
2. Medusa point 1 high — 12p ccd + soc with 4p + 4c + 2lp + unknown rdna 3.5 CU
3. Medusa point 1 — soc with 4p + 4c + 2lp + unknown rdna 3.5 CU
4. Medusa point 2 — soc with less than 4/4/2 cpu & rdna 3.5 cu
5. Medusa point 3 (bumblebee) — soc with 2/2/2 & rdna 3.5 cu

There is a disagreement between the two post.

• 1 CCD only with with 12 classic cores
• 2 CCDs
  1. with 12 classic Cores
  2. with 4 classic cores and 8 dense cores

If the hybrid CCD is real, then it would IMO be better a fit to Medusa point 1 high. 8p + 12c is IMO better suited for mobile than 16p+4c

 

[marees]

There is a disagreement between the two post.

• 1 CCD only with with 12 classic cores
• 2 CCDs
  1. with 12 classic Cores
  2. with 4 classic cores and 8 dense cores

If the hybrid CCD is real, then it would IMO be better a fit to Medusa point 1 high. 8p + 12c is IMO better suited for mobile than 16p+4c

I think others are mostly right on medusa point 1 / hi & medusa halo

However medusa premium is a completely new swim lane category. If this is going to handhelds (z3 extreme) then 4p + 8c makes sense as it is power & budget constrained

By contrast medusa point 1 hi would go to premium notebooks where there is neither power nor budget constraint