Question Zen 6 Speculation Thread

[Kepler_L2]

Is this a good or a bad thing? What does it mean for performance impacts do you think?

Unified generally has better utilization, but requires more area and power than distributed scheduler.

 

[adroc_thurston]

but requires more area and power than distributed scheduler.

yeah so you get a lot less entries.
In any case, this looks like it went back to Zen1/2 scheduler layout?

 

[Kepler_L2]

yeah so you get a lot less entries.
In any case, this looks like it went back to Zen1/2 scheduler layout?

More like Zen3 imo. Zen3 had 4 schedulers (3x ALU + AGU, 1x ALU + Branch). I think Zen6 is 6x ALU + AGU.

 

[Win2012R2]

I think Zen6 is 6x ALU + AGU.

Will that improve integer perf substantially?

 

[adroc_thurston]

I think Zen6 is 6x ALU + AGU.

RETVRN TO K10.5

Will that improve integer perf substantially?

no.
while Zen5 math scheduler was kind of crowded, it's not the main limit.
You have front-end latency, ROB size and int prf to content with mostly.

Pretty sure Zen5 was the first Zen to run out of int regfile in games which is a bit funny.

 

[Win2012R2]

no.

What will it improve then - FP or just more suitable for SMT workloads?

 

[adroc_thurston]

What will it improve then - FP or just more suitable for SMT workloads?

Well it's the int scheduler.
Idk how it impacts FP or SMT suitability.

 

[adroc_thurston]

In any case, this is the first time AMD is diddling schedulers for a derived core.

 

[Win2012R2]

Well it's the int scheduler.

Well if it schedules better then int perf should go up, right? Seems like a drastic change which would be big risk if perf improvements were not good

 

[adroc_thurston]

Well if it schedules better then int perf should go up, right?

Maybe.
math scheduler capacity wasn't a big or real bottleneck for Zen5.
They can split schedulers for fmax reasons or for Cac reduction. Many many many different ways to slice it.

 

[adroc_thurston]

https://twitter.com/x/status/2001686495040585804

oh okay memory scheduler is also GONE.
We're either back to Zen3/4 sched layout, or K10.5.
The latter is the funnier option.

 

[Nothingness]

This reminds me of Intel matrix scheduler: https://dl.acm.org/doi/pdf/10.1145/1273440.1250704
Not saying AMD are doing such an implementation, just that the unified scheduler discussion made me think about what Intel used to do (or still do?) 🙂

 

[adroc_thurston]

just that the unified scheduler discussion made me think about what Intel used to do (or still do?)

ah no LNC ditched unified scheduler and also fixed the port favela that's been with us since P6.
Didn't make the core any better, unfortunately.

 

[CouncilorIrissa]

https://twitter.com/x/status/2001653437583556972

Grok, find team B's fingerprints on this change.

 

[Cheesecake16]

https://twitter.com/x/status/2001653437583556972

Oh awesome, my speculation, at least for the integer scheduler, looks to likely be wrong and that's great!
I do love when I get shit wrong because that means I get to ask questions and learn more about why they did what they did... and I do like interesting twists and this is definitely an interesting twist...

 

[adroc_thurston]

Oh awesome, my speculation, at least for the integer scheduler, looks to likely be wrong and that's great!
I do love when I get shit wrong because that means I get to ask questions and learn more about why they did what they did... and I do like interesting twists and this is definitely an interesting twist...

wanna bet on i$ size now?

 

[AMDK11]

It's amazing how AMD, for the first time in its history, introduced a unified scheduler for 6 ALUs and a separate one for 4 AGUs in Zen5, only to return to the Zen4 scheduler in the next generation of Zen6. That means 6 schedulers, each supporting 1 ALU + 1 AGU, or most of them.

I'm curious about the entire Zen6 core and what other changes have been made compared to Zen5.

 

[Cheesecake16]

https://twitter.com/x/status/2001686495040585804

oh okay memory scheduler is also GONE.
We're either back to Zen3/4 sched layout, or K10.5.
The latter is the funnier option.

I am really interested if they have added 2 more AGUs... because that would be up to 6 memory ops per cycle which is quite spicy IMO...

wanna bet on i$ size now?

I am going to assume it's the same 32KB as Zen 2-5 but I am kinda really hoping for 48+ KB... Maybe 64KB... maybe...

 

[Geddagod]

Simple, you are having to feed a much larger frontend... you expect more L1i misses assuming the same structure size...

But by such a large margin though?
Do we have any reference to other architectures that kept the same L1i capacity but massively increased the front end? GLC vs SNC could be a good comparison, considering they also doubled the L1i bandwidth, kinda like Zen 5 due to the 2 ahead BP?

So that is very dependent on the workload, for example compiling the Linux Kernel the L2 BTB overrides went down from about 12.86 MPKI to about 3 MPKI... where as the L1 iTLB misses went up which again isn't surprising considering that the L1 iTLB size didn't change from Zen 4 to Zen 5...

The only specint2017 subtest where L2 BTB overrides went down in Huang's testing was 500.perlbench 2. 500.perlbench 1 and 3, as well as all the other specint subtests he ran, saw a large L2 BTB override increase.

I am going to assume it's the same 32KB as Zen 2-5 but I am kinda really hoping for 48+ KB... Maybe 64KB... maybe...

Maybe a double node jump allows them to increase capacity. Intel did increase L1i capacity from GLC to RWC when they shrunk from Intel 7 to Intel 4.

 

[poke01]

This makes Zen5 such a unique design.

Could it they are going back to previous designs because Zen6 is going to used in more client focused products as well?

 

[adroc_thurston]

Maybe a double node jump allows them to increase capacity

oh nyo area isn't the problem.
They're just fmaxxing to the gills.

Could it they are going back to previous designs because Zen6 is going to used in more client focused products as well?

no. speed is life.

 

[eek2121]

In any case, this is the first time AMD is diddling schedulers for a derived core.

😉

 

[adroc_thurston]

😉

Oshiete, eep-sempai

 

[AMDK11]

So it turns out that Zen6 is a bigger change than just removing bottlenecks + slightly expanding the core.

 

[Bigos]

inb4 Zen 6 is actually based on Zen 4 (Zen 3 line lives on!).

In all seriousness, I am looking forward to hearing more details.