Question Zen 6 Speculation Thread

[marees]

for the target Market of MDS price matters more and MDS is N3P which had wafer price increased already couple of times PTL is relatively like 90mm2 for the 4+0+4 die and for the Intel 3 iGPU Die is like 20-30mm2 and 48mm2 for N6 IOD plus advanced packing MDS will be monolithic most likely 140-150mm2 N3P

I believe you are referring to MDS-1

There is also MDS-3 (Bumblebee). This has already appeared on a leaked rodmap

MDS-2 is later / scrapped — likely on a different cheaper / power optimized node, per MLID

 

[poke01]

Intel created the 4Xe core SKUs to be primarily used with dGPUs from Nvidia.
These are also not -HX parts but -H. The X7/X9 denotes the number of GPU cores being 12. These 12 core parts will very good for handhelds where dGPUs are not used and for thin and lights where users still want a good iGPU but don't want a dGPU for noise or battery life reasons.

Mudusa Halo will be more expensive than any high end PTL-H SKU. Its a different class of product. What we need to be looking as a end customer is the prices of high end PTL and Medusa Point when both are available. PTL should be much cheaper as it will be a year old by the time Zen6 mobile launches.

 

[Joe NYC]

What we need to be looking as a end customer is the prices of high end PTL and Medusa Point when both are available. PTL should be much cheaper as it will be a year old by the time Zen6 mobile launches.

My understanding of PTL SKUs is that there will be 3 sets:
1. Low CPU core, Low graphics
2. High CPU cores, Low graphics
3. High CPU cores, High graphics

Medusa Point (MDS1) low will be priced somewhere between #1 and #2. Likely closer to #1 due to better cost structure, avoiding expensive packaging.

 

[Tangopiper]

My understanding of PTL SKUs is that there will be 3 sets:
1. Low CPU core, Low graphics
2. High CPU cores, Low graphics
3. High CPU cores, High graphics

Medusa Point (MDS1) low will be priced somewhere between #1 and #2. Likely closer to #1 due to better cost structure, avoiding expensive packaging.

I think you are right, MDS1-lo is absolutely going for volume. It's a very cost optimised part directly replacing KRK1.

MDS1-hi will be the more premium offering with the N2-family CCD glued on.

MDS3/Bumblebee is the KRK2 replacement that will sit in low cost business laptops most likely, and anything super power/thermal constrained.

MDSP (if it still exists) for the Premium thin & lights (and handhelds, but very secondary market) that need more GPU power. More of an Apple M6 & 7 competitor, I don't expect NVL-H 12 Xe3P version to get very close to this in GPU performance.

MDSH for high performance laptops and mini-PCs, just like STXH.

I think the competitive landscape probably looks something like this:
NVL-U vs. MDS3/Bumblebee
NVL-H (4 Xe3) vs. MDS1
NVL-H (12 Xe3P) vs. MDSP
NVL-AX vs. MDSH (NVL-AX probably cancelled)

Razer Lake in 2027 doesn't sound like much of an upgrade, so AMD should remain competitive with MDS family. Only unknown is time to market for Intel + NVIDIA offerings. But that sounds like 2028+ time frame.

 

[Jan Olšan]

If NVL is 52c, Zen6 is 26c. If Zen6 is 24c, NVL is 48c.

Will the desktop IOD have LP cores? I think MLID suggested it won't have them, is there some good info known about this?

 

[adroc_thurston]

Will the desktop IOD have LP cores?

You can just ignore them since LP clusters just can't contribute any real perf at DT power envelopes.

Intel created the 4Xe core SKUs to be primarily used with dGPUs from Nvidia.

see the problem here is that PTL CPU perf is ~Raptor. Gaming is there or worse.

PTL should be much cheaper as it will be a year old by the time Zen6 mobile launches.

it would also be much, much slower.
Cheap ain't worth anything if you suck.

 

[Jan Olšan]

You can just ignore them since LP clusters just can't contribute any real perf at DT power envelopes.

I'm not quite asking about that because of performance. They could help with power usage (and noise) in low loads and during idle, which are IMHO the one area where the current AMD desktop offerings are weakest.
And obviously, if there is a laptop version (Gator Range?), they could help a lot in noise and battery life, if they were in the IOD and worked well...

 

[DrMrLordX]

Do the Range CPUs use meaningfully less power than similarly-positioned desktop CPUs? I got the impression those chips were mostly for DTRs.

 

[adroc_thurston]

I got the impression those chips were mostly for DTRs.

the key world here is 'were'.

 

[Joe NYC]

the key world here is 'were'.

So is that line, and that socket retired for Zen 6?

 

[adroc_thurston]

So is that line, and that socket retired for Zen 6?

no, gator range can be stuffed everywhere compared to Dragon/Fire.

 

[poke01]

These LP zen6 core how low do they go?

<0.5w?

 

[adroc_thurston]

These LP zen6 core how low do they go?

idk.

<0.5w?

Unlikely, sub-500mW is a real LITTLE territory.
800-1000mW probably.

 

[DrMrLordX]

the key world here is 'were'.

Huh, interesting. That certainly shakes up the mobile lineup for Zen6.

 

[Abwx]

idk.

Unlikely, sub-500mW is a real LITTLE territory.
800-1000mW probably.

A Zen 1 2500U/3500U drain 0.8W when the laptop is plugged to the main and 0.6W on battery, and that s with wifi connected internet, if built with say N4P those numbers would be cut by a 3 factor.

 

[adroc_thurston]

A Zen 1 2500U/3500U drain 0.8W when the laptop is plugged to the main and 0.6W on battery, and that s with wifi connected internet, if built with say N4P those numbers would be cut by a 3 factor.

oh no I don't mean standby, I mean active idle power.

 

[Abwx]

oh no I don't mean standby, I mean active idle power.

That s not stand by, the CPU is running normaly, task manager is not at 0% with HVinfo among others consuming some light power, antivirus and all background tasks are also running, task manager say about 150 processes and 2000 threads.

 

[adroc_thurston]

That s not stand by, the CPU is running normaly, task manager is not at 0% with HVinfo among others consuming some light power, antivirus and all background tasks are also running.

That's still not active idle, you have no tasks in the foreground (especially anything powerhungry like jabbascript).

 

[Abwx]

That's still not active idle, you have no tasks in the foreground (especially anything powerhungry like jabbascript).

I updated my post, W10 task manager say 150 processes running within 2000 threads, the CPU is at 1.5-1.6GHz, wich is uselessly exessive but guess that s how AMD did set its frequency range.

 

[poke01]

I updated my post, W10 task manager say 150 processes running within 2000 threads, the CPU is at 1.5-1.6GHz, wich is uselessly exessive but guess that s how AMD did set its frequency range.

Can you check with a AV1/VP9 YouTube video?

What’s the CPU consumption now?

 

[poke01]

if anything, Zen 6 should be more efficient in a future AMD Sony handheld as it doesn’t run Windows. That my thought process when asking the low power zen6 question.

Standby and idle are very important for a console handheld. (Something Nintendo does well despite their use of such an old node)

 

[Abwx]

Can you check with a AV1/VP9 YouTube video?

What’s the CPU consumption now?

Of course that power will increase with a Youtube video since that s no more idling, still that s only 3.3W on average despite the CPU and hardware video decoding block being very old in respect of current ones, average CPU usage is about 12% and GPU 13%, so decoding is shared by the CPU along with the GPU s decoding block, FTR the SoC s max TDP is limited to 22-23W wich is in line with the measured CPU/GPU total usage.

Edit : Anyway Zen 6 should have very low numbers not only because of the process but
also thanks to decoding being 100% computed by a hardware decoding block, guess that it s already the case with KRK.

 

[DisEnchantment]

How did they get >1.7x perf uplift?

Efficiency is also >1.7x which mean same 500W TDP.

• 8x IF links vs 12x on Turin Dense, so lesser number of links to power.
• 2.5D packaging to bring immense power savings in signalling
• New process for IOD for more efficiency
• But signalling rate is higher at 64 Gbps vs 36 Gbps on Turin D

They would need to bring IOD power usage really down to the 60W - 80W to allow around 1.65W< per core for 256 cores in same SoC at 500W. Below that honestly seems difficult considering all the various functions in the IOD.

If they can do <1.65W per core they would need all the power efficiency gains from N2. At minimum 1.1x efficiency per Core.

But they need frequency gains too to get to the 1.7x perf gain.

1.1x power efficiency gain on top of 1.1x frequency gain would be something of an optimistic outcome from the N2 process jump.

1.33x cores * 1.1x frequency * 1.18x perf/clock = 1.73x perf uplift

If there is indeed no increase in TDP, the clocks would be conservative to keep efficiency high which means the perf per clock would be quite high. I would suspect high teens.

Another thing I suspect is additional 2x FP pipes (new AI pipelines by Papermaster, suggesting at least 2x) something new since Z3. This would bring some easy gains in common benches like cinebench and stuff.

 

[adroc_thurston]

Efficiency is also >1.7x which mean same 500W TDP.

it's 600W.

But signalling rate is higher at 64 Gbps vs 36 Gbps on Turin D

there is no link, just SDPs and wires.
In any case, you forgot to account for a titanic membw bump.

 

[DisEnchantment]

it's 600W

That sounds too optimistic, 9965 is 500W for 192 Cores.
You need 2.04x perf increase for 1.2x more power to get 1.7x efficiency.
Need 50% more perf per core even if power use goes up.