Question Zen 6 Speculation Thread

[Joe NYC]

It's never that easy (core's bigger and other things).
But 15% fmax is doable.

That's what I have been thinking. 15%, which corresponds to 6.5 GHz should be considered quite safe target, and anything over that would be a nice bonus.

 

[adroc_thurston]

That's what I have been thinking. 15%, which corresponds to 6.5 GHz should be considered quite safe target, and anything over that would be a nice bonus.

Yea.
Low-mid teens IPC plus 15% fmax and you have a contender.

 

[inquiss]

Plus more power to the cores from lower static power draw from the IO die. Not loads but will help. Plus cache. Gonna be a gaming beast.

 

[adroc_thurston]

Plus more power to the cores from lower static power draw from the IO die. Not loads but will help. Plus cache. Gonna be a gaming beast.

Yeah more stuff adds up.
It worked for Zen2/Zen4 and it'll work here too.

 

[Joe NYC]

Yea.
Low-mid teens IPC plus 15% fmax and you have a contender.

Zen 6.66 confirmed

 

[adroc_thurston]

Zen 6.66 confirmed

Idk but it'll be good enough.

 

[Timorous]

Zen 6.66 confirmed

It is the number of the beast after all.

 

[Josh128]

It is the number of the beast after all.

So you are saying Zen 6 will be a beast?

 

[Doug S]

N2 family is N2, N2p, N2x and A16.
There are no vanilla N2 designs, it's N2p and on.

What do you think A20/A20P will be, if not a "vanilla N2 design"? They can't use N2P, even if it follows N2 by only six months that's nowhere near soon enough to deliver finished chips in products by next September.

 

[adroc_thurston]

What do you think A20/A20P will be

N2p.

They can't use N2P, even if it follows N2 by only six months that's nowhere near soon enough to deliver finished chips in products by next September.

See there's a majick trick being done here.
N2 and N2p are fully design rule compatible so early adopters like AMD tape out A0 on N2 and write the final stepping mask set on N2p.

 

[DrMrLordX]

Marketing still doesn't work that way. The top SKU's have a price bracket.

NV took the price brackets in the dGPU space and blew them to smithereens. Now we have $3k halo video cards. The same could happen to DiY CPUs if Intel continues floundering.

 

[Doug S]

N2p.

See there's a majick trick being done here.
N2 and N2p are fully design rule compatible so early adopters like AMD tape out A0 on N2 and write the final stepping mask set on N2p.

Optical shrink nodes are always design rule compatible. Why didn't everyone who designed on N3E do the same to get N3P wafers?

 

[adroc_thurston]

Why didn't everyone who designed on N3E do the same to get N3P wafers?

They probably did.

 

[eek2121]

I think that everyone needs to start warming up to the idea that Zen 6 desktop is going to get walloped by NVL 52c in MT testing.

Not going to happen. They will be pretty close in terms of performance.

The AMD cores will clock much higher than the Intel ones. Remember , the E cores aren’t designed to clock high to begin with, and the P cores aren’t designed power hungry.

AMD effectively has twice the amount of power per core available, SMT, and they have a more efficient core design.

 

[Fjodor2001]

Not going to happen. They will be pretty close in terms of performance.

The AMD cores will clock much higher than the Intel ones. Remember , the E cores aren’t designed to clock high to begin with, and the P cores aren’t designed power hungry.

AMD effectively has twice the amount of power per core available, SMT, and they have a more efficient core design.

For MT and power constrained, better to have many cores at low frequency than few cores at high frequency. Optimal points on v/f curve and all that.

 

[vanplayer]

I think that everyone needs to start warming up to the idea that Zen 6 desktop is going to get walloped by NVL 52c in MT testing.

I don't know how you define 'wallop', but I'm 100% sure Zen6 24C will stand between Ultra7 & Ultra9 of NVL, I'm afraid it's far from being 'wallop'.

cough, guys might start estimating Zen6 MT perf after reading this message

 

[adroc_thurston]

For MT and power constrained, better to have many cores at low frequency than few cores at high frequency. Optimal points on v/f curve and all that.

That only works if your CPU IP is efficient. Intel's isn't.

cough, guys might start estimating Zen6 MT perf after reading this message

Venice is 1.8x-ish with 33% moar cores and 20% more power with a single shrink.
Olympic Ridge is ??? with 50% more cores and 0% more power with two shrinks.

You can also proxy it to Zen3 -> Zen4 nT bump, which was 30-40% iso CC if memory serves me right.

 

[reaperrr3]

For MT and power constrained, better to have many cores at low frequency than few cores at high frequency. Optimal points on v/f curve and all that.

Again:
What kind of "MT" are we even talking about?
Mass-encoding/decoding videos?
CPU-crypto-mining by kids whose oblivious parents are footing the (power) bills?
Semi-professional workloads by people who would otherwise get a workstation CPU?

Games almost never have more than 6-12 heavy threads, and virtually all other consumer-relevant workloads usually aren't this demanding in the first place.

All that Intel will accomplish with NVL-52c will be to cannibalize some of AMD's (and their own) low-end workstation SKUs, and perhaps give a small demography of richer Intel shills an excuse to return to Intel because they're "first" in something again, no matter useless that something is for them 99.8% of the time.
That's about it.

 

[jpiniero]

Again:
What kind of "MT" are we even talking about?
Mass-encoding/decoding videos?

Cinememe.

 

[Kepler_L2]

That only works if your CPU IP is efficient. Intel's isn't.

Venice is 1.8x-ish with 33% moar cores and 20% more power with a single shrink.
Olympic Ridge is ??? with 50% more cores and 0% more power with two shrinks.

You can also proxy it to Zen3 -> Zen4 nT bump, which was 30-40% iso CC if memory serves me right.

Zen3 MT clocks were very power limited though

 

[adroc_thurston]

Zen3 MT clocks were very power limited though

And Zen4 ones were hampered with terrible AM5 thermals.

 

[Fjodor2001]

Again:
What kind of "MT" are we even talking about?
Mass-encoding/decoding videos?
CPU-crypto-mining by kids whose oblivious parents are footing the (power) bills?
Semi-professional workloads by people who would otherwise get a workstation CPU?

Games almost never have more than 6-12 heavy threads, and virtually all other consumer-relevant workloads usually aren't this demanding in the first place.

All that Intel will accomplish with NVL-52c will be to cannibalize some of AMD's (and their own) low-end workstation SKUs, and perhaps give a small demography of richer Intel shills an excuse to return to Intel because they're "first" in something again, no matter useless that something is for them 99.8% of the time.
That's about it.

The disputed claim was which CPU will be fastest in max MT workloads, Zen6 24C/48T vs NVL 48C. So the assumption is that all 48T will be used for that comparison.

 

[adroc_thurston]

The disputed claim was which CPU will be fastest in max MT workloads, Zen6 24C/48T vs NVL 48C. So the assumption is that all 48T will be used for that comparison.

Just model the perf for both.
Olympic Ridge you can proxy off Venice. NVL you'll need some guesswork.

 

[Fjodor2001]

That only works if your CPU IP is efficient. Intel's isn't.

For Zen6 vs NVL-S we can only guesstimate though, since a lot is unknown.

 

[adroc_thurston]

For Zen6 vs NVL-S we can only guesstimate though, since a lot is unknown.

You can model it.