Question Zen 6 Speculation Thread

[adroc_thurston]

On the other hand, I am not sure what the actual effect of 96 MB -> 144(?) MB will going to be.

Less L3 misses == more good stuff.

 

[LightningZ71]

Save for very specific circumstances, the increase in the base CCD from 32 to 48MB of L3 will be more impactful to more games vs. the previous Gen product. On desktop. Where they aren't aggressive regulating every drop of power. The d2d interface should have somewhat improved latency over Zen5 as well. When you combine those two things with likely being better able to make use of the full spec bandwidth of 8000 rated RAM, should it be affordable, I can't see where ZEN6 won't be a noticeable improvement over vanilla Zen5 for games, and that's before you account for higher clocks and better core IPC (not related to memory subsystem improvements).

 

[adroc_thurston]

The d2d interface should have somewhat improved latency over Zen5

Lmao no.

 

[DrMrLordX]

Less L3 misses == more good stuff.

It'll help applications where the large L3 is already making a difference, presumably. But what will be interesting to see is how many applications/games that currently don't respond well to the X3D treatment will suddenly start performing better once the L3 size goes up.

 

[ondma]

Well, when adding SMT into the mix, it’s not really only fast vs slow cores, but fast vs slow threads we should be talking about.

The point was that once you go past 12T on 12C/24T Zen6, those additional threads will be SMT threads, which are much slower than e.g. E cores that some have been complaining about.

Yeah, but I thought we were talking about gaming. I dont think the E cores are utilized in gaming, so like I said before, you are looking at 12 cores plus HT, vs 8 cores without.

 

[Fjodor2001]

Yeah, but I thought we were talking about gaming. I dont think the E cores are utilized in gaming, so like I said before, you are looking at 12 cores plus HT, vs 8 cores without.

12 cores plus HT means 24T. So then why would E cores not be used on an 8P+16E CPU? As soon as going past 8T the E cores will be used.

 

[Markfw]

12 cores plus HT means 24T. So then why would E cores not be used on an 8P+16E CPU? As soon as going past 8T the E cores will be used.

Zen 6 has no P-cores or e-cores, only regular cores and SMT threads, big difference.

edit: I read above. You also thinks smt threads are slower/worse than e-cores. Not true also, most of the time.
They run at the core speed of the non-smt core, but don't have all the same resources sometimes, but they do have all the capability, like avx-512.

Its apples to oranges comparison.

 

[adroc_thurston]

But what will be interesting to see is how many applications/games that currently don't respond well to the X3D treatment will suddenly start performing better once the L3 size goes up.

Stuff that's not catastrophically membound will enjoy freq bumps and other assorted core improvements.

 

[regen1]

Yeah, but I thought we were talking about gaming. I dont think the E cores are utilized in gaming, so like I said before, you are looking at 12 cores plus HT, vs 8 cores without.

E-cores are utilized in gaming(and also other tasks) as and when required.

 

[LightningZ71]

Lmao no.

I thought we had determined that the CCD links in Strix Halo were less than stellar due to aggressive power management?

 

[adroc_thurston]

I thought we had determined that the CCD links in Strix Halo were less than stellar due to aggressive power management?

No and idk why you think power management would be any less aggressive anywhere else.

 

[OneEng2]

No, just no. When was the last time you saw an ad from Intel? This hasn't been a thing for 20 years or so with perhaps Centrino.

Agree; however, you don't need to pay anyone to paste a big sticker on the laptop saying "52 cores".

That's the same thing.

Power efficient designs and high clock speed designs are NOT the same thing. They are quite different. Explain this absurd statement.

Yupp, 8C will be the Ryzen 5 Zen6 peasant SKU. Then 12-24C SKUs in the rest of the range.

Since the CCD has 12 cores, we might see 6 as the bargain part and go up from there by pairs up to 12 (6,8,10,12). I have a feeling that dual CCD's will come at a premium and might be limited to only higher core counts. We will see .

Someone gotta pay for all dat N2p.
That someone is (You).

That isn't at all how market pricing works. The top tier price doesn't change just because the top tier chip got better. Look up a little ECON 101.

You gotta pay the winner a proper toll and all.

Many words but all that matters in DIY DT is 1t and gaming perf.

DIY is only a tiny portion of the x86 market and a sliver of the revenue and profit. "All that matters" is data center where 85% of AMD's profit was from last quarter.

I dont see Zen 6 gaming having much improved chops over Zen 5. Mostly in line with clock speed increases.

I agree. IPC improvements will be slim. The clock speed increase will likely be a bigger factor.

 

[Joe NYC]

It'll help applications where the large L3 is already making a difference, presumably. But what will be interesting to see is how many applications/games that currently don't respond well to the X3D treatment will suddenly start performing better once the L3 size goes up.

It didn't "just happen" with Zen 5, when we are starting to see big performance advantages for V-Cache across the board, including non-gaming applications.

It was because when the clock speed deficit between V-Cache and non-V-Cache narrows or disappear, everything performs better.

Probably more of the same with Zen 6. Clock speed deficit of V-Cache parts will probably narrow further or completely disappear. And then, extra on-board L3 + extra V-Cache...

 

[Fjodor2001]

Since the CCD has 12 cores, we might see 6 as the bargain part and go up from there by pairs up to 12 (6,8,10,12).

Are we really expecting there to be so many 12C dies with non-functional cores that they’ll be binning as 6, 8, 10 and 12 core SKUs?

Or do you mean that they’ll intentionally disable working cores just to maintain some market segmentation? E.g. even if a die has 10 working cores, they will disable 4 of them intentionally and sell it as a 6C SKU?

 

[Thunder 57]

Agree; however, you don't need to pay anyone to paste a big sticker on the laptop saying "52 cores".

I don't think they would put 52C variants in laptops. That would almost certainly be bad for battery life and reviews would hold that against them. Especially under load.

Since the CCD has 12 cores, we might see 6 as the bargain part and go up from there by pairs up to 12 (6,8,10,12). I have a feeling that dual CCD's will come at a premium and might be limited to only higher core counts. We will see .

Too many SKU's. disabling half the CCD to put out a six core vairant would be wasteful. Mobile Zen 6 could cover that market like it did with low end Zen 3. I think eight and 12 would be enough. Then take your pick of 16/18/20 and a 24 core model. Maybe they do 12, 16, 20, 24. Or maybe they keep it simple and offer 12, 18, 24. Ask Adroc if you're willing to "beg", surely he knows .

 

[DrMrLordX]

That isn't at all how market pricing works. The top tier price doesn't change just because the top tier chip got better. Look up a little ECON 101.

It is when there's no serious competition. Take a look at 5090 prices . . .

It didn't "just happen" with Zen 5, when we are starting to see big performance advantages for V-Cache across the board, including non-gaming applications.

It was because when the clock speed deficit between V-Cache and non-V-Cache narrows or disappear, everything performs better.

Probably more of the same with Zen 6. Clock speed deficit of V-Cache parts will probably narrow further or completely disappear. And then, extra on-board L3 + extra V-Cache...

Yeah but I'm talking about stuff that may become a little bit less memory bound once L3 grows again.

 

[adroc_thurston]

Power efficient designs and high clock speed designs are NOT the same thing

Uhhhh.
Alright talking to you is pointless.

That isn't at all how market pricing works. The top tier price doesn't change just because the top tier chip got better. Look up a little ECON 101.

It's not that it got better.
BoM went up and the one paying for it is (You).

 

[adroc_thurston]

https://twitter.com/x/status/1993676487057354824

Hell yeah TSM is finally being honest.

 

[OneEng2]

Are we really expecting there to be so many 12C dies with non-functional cores that they’ll be binning as 6, 8, 10 and 12 core SKUs?

Or do you mean that they’ll intentionally disable working cores just to maintain some market segmentation? E.g. even if a die has 10 working cores, they will disable 4 of them intentionally and sell it as a 6C SKU?

My assumption (which may be incorrect) is that AMD will want to sell every single die they can to counter the increased cost of N2.

I was speculating on how they would go about doing that.

I don't think they would put 52C variants in laptops.

Fair. Even in Laptops, 26c sounds pretty impressive when AMD may offer only 12.

Too many SKU's.

Perhaps.

It is when there's no serious competition.

Marketing still doesn't work that way. The top SKU's have a price bracket.

In DC, there is different calculus. Higher performance and throughput actually pays off. Not so with consumer.

Zen 5 launched its top SKU at $649. If AMD were to make a Zen 6 SKU priced >$800, my guess is that it wouldn't sell enough volume to pay for the overhead of creating a separate SKU.

Those of us that have been around a while have already seen what happens in the face of one company dominating the other. Intel had this for a long time back in the 90's. Things simply stagnated. The top SKU was still the same price, but every year the update was a tiny 50Mhz IIRC. No innovation, no moving forward, just lots of profit taking. AMD simply sold bargain parts back then.

It's not that it got better.
BoM went up and the one paying for it is (You).

Again (sigh) do some research into ECON 101.

 

[adroc_thurston]

Again (sigh) do some research into ECON 101.

Olympic Ridge as a package is much more expensive than Granite Ridge and (you) will pay for that. It's normal.

 

[Josh128]

https://twitter.com/x/status/1993676487057354824

Hell yeah TSM is finally being honest.

This is exactly why you aint getting 5GHz all core on 24 core SKU@ 200W. Also, whats A16 SPR? Its coming before N2X?

 

[adroc_thurston]

This is exactly why you aint getting 5GHz all core on 24 core SKU@ 200W.

Is this a goalpoast move or idk wtaf is that.
Since you're getting moar than that in a 48c F EPYC too, and that's 350W all in all.

Also, whats A16 SPR?

N2p derivative with BSPDN.

Its coming before N2X?

Indeed.

 

[MS_AT]

Olympic Ridge as a package is much more expensive than Granite Ridge and (you) will pay for that. It's normal.

btw, any idea if they are planning to do the same (too small BIOS(TM)) story as they did with Zen3? as it seems the latest mobo offerings are advertising 64MB bios chips, so I wonder if they will once again delay the support for older mobos...

 

[adroc_thurston]

btw, any idea if they are planning to do the same (too small BIOS(TM)) story as they did with Zen3?

No.

as it seems the latest mobo offerings are advertising 64MB bios chips, so I wonder if they will once again delay the support for older mobos...

It's a maymay, you're getting full Z6 support either way.
Obviously, you're gonna run crippled mem speeds versus what medusaDT is actually rated for, but that's no biggie.

 

[OneEng2]

Olympic Ridge as a package is much more expensive than Granite Ridge and (you) will pay for that. It's normal.

Marketing 101. Different MARKET segments have different pricing. The example you just gave are two very different market segments so OF COURSE the pricing is different.

ECON 101. Cost of a product DOES NOT dictate price. Market value DOES.

Cost only effects profitability. Not price.