Question Zen 6 Speculation Thread

[adroc_thurston]

ECON 101. Cost of a product DOES NOT dictate price. Market value DOES.

Cost only effects profitability. Not price.

Again, you'll pay more to win more. If you're poor you can always buy Zen5. They're the same platform, after all.

Reality's hard but someone will pay for the death of Moore's Law, and that someone is (You). Enjoy!

 

[Claudiovict]

Zen 6 laptop CPUs will have any difference in iGPU department compared to Zen 5?

 

[adroc_thurston]

Zen 6 laptop CPUs will have any difference in iGPU department compared to Zen 5?

It's on N3p so they go faster, clock-wise.
Otherwise unchanged.

 

[Fjodor2001]

Again, you'll pay more to win more. If you're poor you can always buy Zen5. They're the same platform, after all.

Reality's hard but someone will pay for the death of Moore's Law, and that someone is (You). Enjoy!

You had the same reasoning for Zen5 and predicted the 16C (then assumed to be named 8950X) to cost $999. Remember this:

They'll charge $999 for 8950X instead.
lack of comp isn't good either way.

Yes very realistic.
You're gonna pay $999 for 16c.

Then the launch price turned out to be $649. So 35% lower, or 65% of the predicted $999 price.

If we use that to calibrate your Zen6 price estimates, then we get this:
24C predicted $849, actual $849*65% = $552
8C predicted $399, actual $399*65% = $259

 

[adroc_thurston]

You had the same reasoning for Zen5 and predicted the 16C (then assumed to be named 8950X) to cost $999. Remember this:

Then the launch price turned out to be $649. So 35% lower, or 65% of the predicted $999 price.

This is adorable cope.
Now do something useful and try modeling Zen6 perf, both 1t and nT, preferably with voltage reference points.

 

[Claudiovict]

It's on N3p so they go faster, clock-wise.
Otherwise unchanged.

the high-end ones will also be on N3P? Like the sucessor of 9955HX3D, i would expect it to be on 2nm

 

[Kepler_L2]

btw, any idea if they are planning to do the same (too small BIOS(TM)) story as they did with Zen3? as it seems the latest mobo offerings are advertising 64MB bios chips, so I wonder if they will once again delay the support for older mobos...

64MB BIOS is for Zen7 support

 

[adroc_thurston]

the high-end ones will also be on N3P? Like the sucessor of 9955HX3D, i would expect it to be on 2nm

You mean Gator Range? That's N2p, it's all CCDs.

 

[OneEng2]

You had the same reasoning for Zen5 and predicted the 16C (then assumed to be named 8950X) to cost $999. Remember this:


Then the launch price turned out to be $649. So 35% lower, or 65% of the predicted $999 price.

If we use that to calibrate your Zen6 price estimates, then we get this:
24C predicted $849, actual $849*65% = $552
8C predicted $399, actual $399*65% = $259

Thanks for looking that up.

Aside from $>800 being way outside the market price today for that market segment, it is nice to see that similar (wrong) predictions were made for Zen5.

Note: I do agree that, like Zen 5, the introductory price for Zen 6 will be higher than the current 9950X (currently around $510-$525).

Launch price of the 9950X was $649. Considering inflation, it wouldn't be out of the question to se $699 at launch; however, I think market demand (especially for desktop) is down so perhaps $599-$649?

It is also dependent on supply. If AMD has yield issues and can't supply the demand, the price will go up (and volume sold go down as is typical in supply and demand curves).

I think that it is flat out crazy to think AMD or Intel can command >$800 for ANY desktop chip in today's market.

5950X launched at $799 ..... BUT that was during COVID and the chip shortage debacle. This was the highest price in consumer processor history.

So shy of another global pandemic, I'll stick with sub $700 at launch for the flagship.

 

[511]

Zen 6 has no P-cores or e-cores, only regular cores and SMT threads, big difference.

edit: I read above. You also thinks smt threads are slower/worse than e-cores. Not true also, most of the time.

Comparing a ST Thread to real core is not easy it sounds the core thread shares resources with the core like you said an E core can be better for many stuff while HT can be better for other stuff you need to know your workload to pick no clear winners.

They run at the core speed of the non-smt core, but don't have all the same resources sometimes, but they do have all the capability, like avx-512.

Its apples to oranges comparison.

AVX-512 will be in next gen E/P cores a much better version(no shenanigans) and APX.

 

[StefanR5R]

Re #7,834: In a simple world, economy is the same as market economy, and market economy is nothing but supply and demand. It's world number 101.

 

[luro]

Cost only effects profitability. Not price.

Only when comparable competition exists.

Any serious company will raise its prices when costs go up and it has room to do so, either due to a lack of competition or because competitors are also raising prices. This is basic pricing and finance.

 

[Thunder 57]

Zen 5 launched its top SKU at $649. If AMD were to make a Zen 6 SKU priced >$800, my guess is that it wouldn't sell enough volume to pay for the overhead of creating a separate SKU.

Those of us that have been around a while have already seen what happens in the face of one company dominating the other.

So what is AMD to do with all those good CCD's? Only put them in 12C chips? There will be enough to go around for 24C chips to make that halo product.

Also you've said it before and here it is again. You're not the only one whose been around awhile. There are plenty of people here with a wealth of experience.

btw, any idea if they are planning to do the same (too small BIOS(TM)) story as they did with Zen3? as it seems the latest mobo offerings are advertising 64MB bios chips, so I wonder if they will once again delay the support for older mobos...

The rumor was the BIOS was larger to include a basic wifi driver so basically force people to install Windows with an Internet connection. I like @Kepler_L2 's answer better because that would mean Zen 7 will be on AM6.

This is adorable cope.
Now do something useful and try modeling Zen6 perf, both 1t and nT, preferably with voltage reference points.

How about admitting you were wrong, just once? Nobody gets it right all the time. Hell, it might make you seem more human/credible. As far as I can tell though, you just like to spew shit with authority and anyone who disagrees is an idiot or needs "meds".

 

[adroc_thurston]

How about admitting you were wrong, just once? Nobody gets it right all the time

I wish.

As far as I can tell though, you just like to spew shit with authority and anyone who disagrees is an idiot or needs "meds".

No, this place is just unfit for any serious discussion for obvious reasons.
There's still like 5 guys here capable of sustaining a technical convo. That guy's not one of them

 

[Joe NYC]

https://twitter.com/x/status/1993676487057354824

Hell yeah TSM is finally being honest.

So TSMC was sandbagging a little bit about N2P?

BTW, who is using N2 rather than N2P? It seems that everyone wants N2P.

 

[adroc_thurston]

So TSMC was sandbagging a little bit about N2P?

N2p is tied to Venice/MI455X shipping schedule.

BTW, who is using N2 rather than N2P? It seems that everyone wants N2P.

Less 'wants' and more like "N2p ramped outside everyone's product refresh cycle". Too late for Apple, too early for AMD.

 

[Doug S]

So TSMC was sandbagging a little bit about N2P?

BTW, who is using N2 rather than N2P? It seems that everyone wants N2P.

If N2P really is following N2 by only six months, then anyone who wants to ship product in 2026 will be using N2. We know Apple will be shipping 100+ million units using N2 class chips next year (plus whatever is going into their servers) so obviously those can't use N2P. Apple has half the initial allocation of N2 wafers, so Nvidia and whoever else has the rest would be the others using N2.

 

[adroc_thurston]

Apple has half the initial allocation of N2 wafers, so Nvidia and whoever else has the rest would be the others using N2.

They don't.
AMD ramps the N2 family (and every node after).

 

[inquiss]

If N2P really is following N2 by only six months, then anyone who wants to ship product in 2026 will be using N2. We know Apple will be shipping 100+ million units using N2 class chips next year (plus whatever is going into their servers) so obviously those can't use N2P. Apple has half the initial allocation of N2 wafers, so Nvidia and whoever else has the rest would be the others using N2.

Don't think Nvidia are even using N2 next year. AMD is the big d*ck swinger for N2

 

[Doug S]

They don't.
AMD ramps the N2 family (and every node after).

Apple having half the N2 wafers has been widely reported. But yeah you know better. "Trust me, bro", right? Get away from us with your nonsense, no believes your bs anymore without proof.

 

[Doug S]

They don't.
AMD ramps the N2 family (and every node after).

Wait, I thought you kept saying that Zen 6 was N2P until you were blue in the face. Eating those words now?

 

[adroc_thurston]

Apple having half the N2 wafers has been widely reported

Chaiwanese yellow press is not "widely reported".

But yeah you know better. "Trust me, bro", right? Get away from us with your nonsense, no believes your bs anymore without proof.

You can ask anyone in the supply chain as in who's the driver for N2, A16 and A14 and you'll get an easy, definitive answer.
You'll also understand why TSM is hiking wafer ASPs.

 

[adroc_thurston]

Wait, I thought you kept saying that Zen 6 was N2P until you were blue in the face. Eating those words now?

N2 family is N2, N2p, N2x and A16.
There are no vanilla N2 designs, it's N2p and on.

 

[Joe NYC]

https://twitter.com/x/status/1993676487057354824

Hell yeah TSM is finally being honest.

BTW, just playing with the numbers:

N5 -> N2 performance @ same power scaling = 1.58 / 1.18 = 1.3389

Zen 4 on N5 (@5.7 GHz) -> Zen 6 on N2 = 5.7 * 1.3389 = 7.63 GHz

 

[adroc_thurston]

Zen 4 on N5 (@5.7 GHz) -> Zen 6 on N2 = 5.7 * 1.3389 = 7.63 GHz

It's never that easy (core's bigger and other things).
But 15% fmax is doable.